A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into FN/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems.

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into FN/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

Provided herein may be an error correction decoder based on an iterative decoding scheme using NB-LDPC codes and a memory system having the same. The error correction decoder may include a symbol generator for assigning an initial symbol to a variable node, a reliability value manager for setting and updating reliability values of candidate symbols of the variable node in current iteration, a flipping function value calculator for calculating a flipping function value by subtracting a function value, related to the updated reliability values of remaining candidate symbols other than a target candidate symbol, from another function value, related to the updated reliability value of the target candidate symbol, in the current iteration, and a symbol corrector for changing the hard decision value to the target candidate symbol when the flipping function value is equal to or greater than a first threshold value in the current iteration.

A method of training artificial intelligence to execute a decoding program of a low density parity check code, which includes steps of: providing check nodes and variable nodes; outputting accessed bit values stored in memory units to the variable nodes; providing initial log-likelihood ratios to the variable nodes; decoding the accessed bit values based on the initial log-likelihood ratios to output decoded bit values at the variable nodes; executing checking programs at the check nodes to determine whether or not the decoded bit values are equal to data bit values to be stored in the memory units, if yes, outputting a correct message, if not, outputting an error message and then executing the next step; initiating an artificial intelligence neural network system to use machine learning to analyze practical log-likelihood ratios; and decoding the accessed bit values based on the practical log-likelihood ratios at the variable nodes.

Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.

Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.

A programmable digital data encoder employs error correcting coding that uses Galois field multiplication logic wherein each bit of the product is produced by first applying pre-calculated mask values or mask values calculated via a processor executing code, and then applying an XOR circuit together with the mask bits from the pre-calculated or generated mask. In one example, a set of Galois field multipliers is used wherein each multiplier in the set includes a plurality of 2-bit input AND gate circuits and an m-bit input XOR gate circuit to produce a bit of the product. In one example, there are m mask values in a mask table wherein m is the symbol width. A different mask value is applied for each bit of the product. The mask values are each m-bits wide, and are stored, for example, in memory as a small look-up table with m m-bit entries or in m m-bit wide registers.

A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.