A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0 is interchanged with a bit y1, a bit b1 is interchanged with a bit y0, and a bit b2 is interchanged with a bit y2.

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word.

Techniques and apparatus are provided for efficiently generating multiple lifted low-density parity-check (LDPC) codes for a range of block lengths and having good performance. A method for wireless communications by a transmitting device generally includes selecting integer lifting values for a first lifting size value Z, selected from a range of lifting size values, wherein the selected integer lifting value is greater than a maximum lifting size value of the range of lifting size values; determining one or more integer lifting values for generating at least a second lifted LDPC code having a second lifting size value based on an operation involving the second lifting size value and the selected one or more integer lifting values for generating the first lifted LDPC code; encoding a set of information bits based on the second lifted LDPC to produce a code word; and transmitting the code word.

Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.

Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation.

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

A data processing device includes decoder circuits, a checker circuit, and a control circuit. The decoder circuits set groups of first sampling points and groups of second sampling points according to an initial transition edge of a first signal, and perform a parallel decoding on the first signal according to the groups of first sampling points and the groups of second sampling points, in order to generate a second signal and a third signal. The checker circuit checks the second signal and the third signal, in order to generate a check result. The control circuit selects at least one of the decoder circuits according to the check result for receiving subsequent data.

A communication system includes a transmitter having an encoder configured to encode input data using FEC codewords and a receiver including a decoder configured to decode the FEC codewords using a parity check matrix. The decoder includes check node processing units each configured to perform a check node computation on an FEC codeword using a different row of the parity check matrix. Each of the check node processing units includes an input computation stage configured to compute initial computation values, a pipelined message memory configured to shift the initial computation values at a predefined clock interval, an output computation stage configured to generate a plurality of check node output messages, a plurality of variable node processing units each configured to perform variable node update computations to generate the variable node messages, and an output circuit configured to generate a decoded codeword based on the variable node messages.