The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

Embodiments of the invention provide a variable node processing unit (31) for a non-binary error correcting code decoder, the variable node processing unit (31) being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit (31) comprises: a sorting and redundancy elimination unit (313) configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.

According to some embodiments, a method in a wireless transmitter comprises: receiving a plurality of bits for a wireless transmission; determining a maximum code block size for the transmission based on code rate, maximum code word size Nmax, and design parameters of the channel code; segmenting the plurality of bits into one or more code block segments such that no one of the one or more code block segments is larger than the determined maximum code block size; and transmitting the one or more code block segments to a wireless receiver. In particular embodiments, the design parameters of the channel code limit the maximum code block size to Kmax for any code rate. The determined maximum code block size may be limited by code rate and Nmax such that the maximum code block size does not exceed code rate times Nmax.

Apparatuses, systems, and techniques to correct errors in information received from a plurality of fifth-generation new radio antennas. In at least one embodiment, codeword information is decoded by a plurality of variable (or vector) nodes and check nodes, where codewords and nodes are divided among processors to be performed in parallel.

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention comprises: a step of generating a multi-edge LDPC code matrix which comprises a high rate code matrix and a single parity check code matrix; and a step of encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix may be configured by connecting a first matrix which is configured as a quasi row-orthogonal structure matrix and a second matrix which is configured as a pure row-orthogonal structure.

A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.

Apparatuses, systems, and techniques to decode encoded data. In at least one embodiment, parts of information for decoding the encoded data is provided to a plurality of processors, and parts of data decoded by the plurality of processors is combined.

Methods, systems, and devices for wireless communications are described. Efficient low-density parity-check (LDPC) scheduling of layered decoding may include receiving a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes, applying a first number of decoding iterations to decoding the message, applying a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, and decoding the message through completion of both the first number of decoding iterations and the second number of decoding iterations. In some cases, only a portion of the number of check nodes is decoded during each of the first number of decoding iterations and all of the number of check nodes are decoded during each of the second number of decoding iterations.

A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.