Low-density parity-check (LDPC) encoded data with one or more errors is received. Information associated with an early convergence checkpoint that occurs at a fractional iteration count that is strictly greater than 0 and strictly less than 1 is received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. At the early convergence checkpoint that occurs at the fractional iteration count, it is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

Provided is an information processing method. The method includes that: first data to be decoded and one or more decoding parameters of the first data are obtained; a basis matrix is determined based on the one or more decoding parameters; a decoding instruction set including a plurality of decoding instructions is determined based on the basis matrix, wherein the plurality of decoding instructions include elements in the basis matrix; and the first data is decoded based on the decoding instruction set. Further provided are an information processing device and a computer storage medium.

Embodiments herein relate to a method performed by a network node for handling a received signal in a communication network. The network node distributes a first number of inputs of a demodulated signal to a first processing core of at least two processing cores and a second number of inputs of the demodulated signal to a second processing core of the at least two processing cores. The network node further decodes the first number of inputs of the demodulated signal by a first message passing within the first processing core, and decodes the second number of inputs of the demodulated signal by a second message passing within the second processing core. The network node further decodes the demodulated signal by performing a third message passing between the different processing cores over a bus that is performed according to a set schedule.

An electronic device is configured to perform a series of low density parity check, LDPC, decoding operations that use at least one basegraph that comprises two or more columns, each column associated with a set of two or more soft bit values. The electronic device includes two or more rotators, each rotator-configured to rotate an order of a subset of two or more soft bit values of the set of two or more soft bit values of a column when activated in an LDPC decoding operation; wherein rotations associated with each column in each basegraph are performed by a particular one of the rotators-of the two or more rotators, wherein each rotator performs rotations for a set of one or more columns, with at least one of the rotators performing rotations for two or more columns in a same basegraph.

The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.

Low-density parity-check (LDPC) encoded data with one or more errors is received. Information associated with an early convergence checkpoint that occurs at a fractional iteration count that is strictly greater than 0 and strictly less than 1 is received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. At the early convergence checkpoint that occurs at the fractional iteration count, it is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

A decoding method for low density parity check (LDPC) code, used to decode an input signal into a correct codeword according to a predetermined LDPC matrix, is provided. The method includes performing a plurality of decoding attempts according to the LDPC matrix within a predetermined number of decoding attempts, the plurality of decoding attempts at least including a first decoding attempt with use of a first decoding schedule and a second decoding attempt with use of a second decoding schedule. The second decoding attempt is adjacently subsequent to the first decoding attempt. The first decoding schedule as a group is not included in the second decoding schedule.

Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.

There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.