Patent classifications
H03M13/114
Computer-implemented method for error-correction-encoding and encrypting of a file
A computer-implemented method for error-correction-encoding and encrypting of a file is provided. The file is split into at least two blocks. The first block is encrypted using a given encryption key. The encrypted first block is encoded twice using a first and second forward error correction code of the first block. Each subsequent block is encrypted by performing an algebraic operation. The encrypted block is encoded twice using a first and second forward error correction code for this block, wherein a cryptographic indexing function provides a set of indices used by the second forward error correction code to produce the second encoded chunk. The first encoded chunks of each encrypted block are outputted. The computer-implemented method enables secure transmission of a file content between low power devices.
HIGH-RATE LONG LDPC CODES
Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices, comprising: receiving a 1×K source word row vector ū; and generating a 1×N codeword vector
Multi-Standard Low-Density Parity Check Decoder
A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.
System and method for multi-path mesh network communications
The disclosed invention provides system and method for multi-path mesh network communications. The network system utilizes multiple communication paths and linearly encoded and disassembled packets through mathematical coding techniques that respectively travel the communication paths. The system includes an encoder, a transmitter, a decoder and a receiver. The encoder receives data from an external source and linearly encodes and simultaneously disassembles the data to generate copackets. None of the individual copackets contain decodable information of the data. The transmitter is coupled to the multiple communication paths and respectively transmits the copackets through different communication paths. The receiver receives the copackets transmitted through the communication paths. The decoder decodes available copackets and reassembles the data from the available copackets if a number of the available copackets are no less than a mathematically calculated number. The reassembled data has the complete information of the data originally transmitted.
METHOD AND APPARATUS FOR DATA DECODING IN COMMUNICATION OR BROADCASTING SYSTEM
An apparatus and method for efficiently decoding a low-density parity-check (LDPC) code in a communication or broadcasting system are provided. The disclosure relates to performing decoding of an LDPC code by using layered scheduling or a method equivalent thereto, and provides an LDPC decoding apparatus and method for improving decoding performance without increasing decoding complexity by applying appropriate decoding scheduling according to structural or algebraic characteristics of an LDPC code.
BANDWIDTH CONSTRAINED COMMUNICATION SYSTEMS WITH FREQUENCY DOMAIN INFORMATION PROCESSING
The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block that processes the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.
Low-density parity-check (LDCP) decoder of reconstruction-computation-quantization (RCQ) approach for a storage device
A device is disclosed. The device may include an input buffer to receive a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message, producing a first high bit width message. A computation circuit may implementing a computation function on the first high bit width message, producing a second high bit width message. A quantization circuit may implementing a quantization function on the second high bit width message, producing a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on an iteration and a layer of the device.
METHOD AND APPARATUS FOR DECODING DATA PACKETS IN COMMUNICATION NETWORK
The present disclosure relates to a method and an apparatus for decoding data packets in communication network. The method comprises receiving one or more data packets related to each of one or more data types; and decoding the one or more data packets using a parity check matrix associated with the corresponding data type, wherein the parity check matrix comprises a plurality of layers, arranged according to a combination of layers which is determined using a reinforcement model.
OUT-OF-ORDER PROCESSING FOR BIT-FLIPPING DECODERS IN NON-VOLATILE MEMORY DEVICES
Devices, systems and methods for improving the convergence of a bit-flipping decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, computing a plurality of flipping energies for each column of a first subset of columns from the plurality of columns of circulant matrices, computing, based on the plurality of flipping energies, one or more metrics, selecting, based on the one or more metrics, a second subset of columns from the first subset of columns in an order that is different from a sequential indexing order of the second subset of columns, determining, based on processing the second subset of columns using a vertically shuffled scheduling operation, a candidate version of the transmitted codeword.
DECODING METHOD, DECODING DEVICE, AND DECODER
Provided are a decoding method, a decoding device and a decoder. The method includes: setting a decoder parallelism P, and splitting soft information of a block to be decoded according to the parallelism P; performing decoding calculation on the block to be decoded according to the split information, and outputting decoded hard bit information; and recombining the hard bit information according to the parallelism P.