A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value

A device for generating a multi-kernel polar code x.sub.N of length N and dimension K on the basis of a first transformation matrix G.sub.N of size N×N that defines a first multi-kernel polar code includes a processor configured to generate a second transformation matrix G′.sub.N of size N×N by permuting the order of at least two columns of a sub-matrix of the first transformation matrix G.sub.N, and generate the multi-kernel polar code x.sub.N an the basis of x.sub.N=u.sub.N.Math.G′.sub.N, wherein u.sub.N=(u.sub.0, . . . , u.sub.N−1) is a vector of size N, with the elements u.sub.i, i=0, . . . N−1, corresponding to an information bit if i∈I, I being a set of K information bit indices, and u.sub.i=0, if i∈F, F being a set of N−K frozen bit indices.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.

In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

A method for performing low density parity check (LDPC) coding of a transmitter in a wireless communication system, according to the present disclosure, may comprise the steps of: acquiring a proto-matrix corresponding to a protograph; on the basis of weights and lifting factors of columns of the proto-matrix, acquiring one or more permuted vectors corresponding to each of the columns, a first permuted vector included in the one or more permuted vectors having been randomly generated; distributing the one or more permuted vectors for each row of a corresponding column; on the basis of the distributed one or more permuted vectors, acquiring a plurality of lifted sub matrices corresponding to a plurality of elements of the proto-matrix; generating a base graph on the basis of the plurality of lifted sub matrices; generating a parity check matrix (PCM) on the basis of the base graph; and performing LDPC coding by using the PCM.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.