Patent classifications
H04L25/0307
Blind classification of modulation scheme of an interfering signal
A technique for wireless signal processing performed at a receiver in a wireless network includes receiving, by a wireless receiver, an orthogonal frequency division multiplexing (OFDM) signal on a shared downlink channel from the wireless network, wherein the OFDM signal includes contribution from a serving cell signal and at least one interfering signal, obtaining an estimate of the serving cell signal, calculating a residual signal by subtracting the estimate of the serving cell signal from the OFDM signal, generating a whitened residual signal by whitening the residual signal, obtaining an estimate of a modulation scheme of the at least one interfering signal by performing a likelihood-based blind classification on the whitened residual signal, and performing further receiver-side processing of the serving cell signal using the estimate of the modulation scheme of the at least one interfering signal.
Optimum phase searching system and method thereof in ethernet physical layer
A system for optimum phase searching in an Ethernet physical layer includes a time recovering circuit and an equalizer. The time recovering circuit includes a loop filter and a time error detector, and the equalizer includes a feed forward equalizer, a slicer and a feed backward equalizer. An optimum phase searching method includes obtaining optimum phases when mean squared errors calculated by the slicer are less than a first threshold, absolute values of mean values of outputs calculated by a time error detector are less than a second threshold, and the outputs are monotonic.
Signal-equalization with noise-whitening filter
Signal equalization is provided, according to certain aspects, by a frequency-domain equalization circuit, a noise-whitening filter and a noise predictor. A sequencer is used to control ordering of the equalization circuit, a noise-whitening filter and a noise predictor. The equalization circuit provides equalization the frequency domain by converging on symbols of the input signal. The noise-whitening filter and the noise predictor filter colored noise from a signal responsive to the equalization circuit. The sequencer controls operation of the noise-whitening filter by detecting an indication of convergence of the symbols from input signal and causing the noise-whitening filter to commence suppression of colored noise from a signal derived from an output by the equalization circuit.
METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
HIGH-SPEED SIGNALING SYSTEMS AND METHODS WITH ADAPTABLE, CONTINUOUS-TIME EQUALIZATION
A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
EDGE BASED PARTIAL RESPONSE EQUALIZATION
A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.
Mitigating interaction between adaptive equalization and timing recovery
System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.
Methods and circuits for asymmetric distribution of channel equalization between devices
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
High-speed signaling systems and methods with adaptable, continuous-time equalization
A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
SYSTEMS, METHODS AND ALGORITHMS FOR RECEIVERS OF DIGITALLY MODULATED SIGNALS
A system and method are disclosed to extract the sequence of symbols of a digitally modulated signal, which jointly recover the symbol synchronism, equalize the transmission channel and mitigate interfering signals. In addition, an algorithm is disclosed to adaptively update the response of finite impulse response filters which recursively computes the filter taps every N samples of the input signal, where N is the ratio between the symbol rate and the sampling rate.