A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

The present disclosure has an object of providing a silicon carbide semiconductor device with high productivity which prevents characteristic degradation occurring when a large current is applied to a body diode. A structure including a SiC substrate, a buffer layer, and a drift layer is classified into an active region through which a current flows with application of a voltage to the SiC-MOSFET, and a breakdown voltage support region around a periphery of the active region in a plan view. The active region is classified into a first active region in a center portion, and a second active region between the first active region and the breakdown voltage support region in the plan view. Lifetimes of minority carriers in the second active region and the breakdown voltage support region are shorter than that in the first active region.

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

In the semiconductor device, a high-concentration diffusion layer and a low-concentration diffusion layer are disposed around a drain diffusion layer of an ESD protection element. The high-concentration diffusion layer is separated from a gate electrode, and a medium concentration LDD diffusion layer is disposed in a separation gap. Variations in characteristics are suppressed by reducing thermal treatment on the high-concentration diffusion layer and a medium concentration diffusion layer.

A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region. The method may further include removing at least some of the pad oxide, cleaning the active region to expose an upper surface thereof and define rounded shoulders of the active region adjacent the STI regions having an interior angle of at least 125°, and forming a superlattice on the active region. The superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor circuit including the superlattice.

A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor.

Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.