A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.

A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

The present disclosure provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (30). The transistor includes a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) disposed on the channel layer (201), and the drain layer (203) and the source layer (202) are vertically distributed on the channel layer (201). The resistance change device (30) is disposed near the drain layer (203). The disclosure reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory.

A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.

Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.

A method of operating a beamline ion implanter may include performing, in an ion implanter, a first implant procedure to implant a dopant of a first polarity into a given semiconductor substrate, and generating an estimated implant dose of the dopant of the first polarity based upon a set of filtered information, generated by the first implant procedure. The method may also include calculating an actual implant dose of the dopant of the first polarity using a predictive model based upon the estimated implant dose, and performing, in the ion implanter, an adjusted second implant procedure to implant a dopant of a second polarity into a select semiconductor substrate, based upon the actual implant dose.

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

A pixel includes a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a floating diffusion node in the protrusion. The pixel further includes a gate structure over the bulk, wherein a top surface of the gate structure is above a top surface of the floating diffusion node. The pixel further includes a photosensitive device in the bulk. The pixel further includes an isolation well surrounding the photosensitive device.

A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.