An apparatus and method of processing a workpiece is disclosed, where a sacrificial capping layer is created on a top surface of a workpiece. That workpiece is then exposed to an ion implantation process, where select species are used to passivate the workpiece. While the implant process is ongoing, radicals and excited species etch the sacrificial capping layer. This reduces the amount of etching that the workpiece experiences. In certain embodiments, the thickness of the sacrificial capping layer is selected based on the total time used for the implant process and the etch rate. The total time used for the implant process may be a function of desired dose, bias voltage, plasma power and other parameters. In some embodiments, the sacrificial capping layer is applied prior to the implant process. In other embodiments, material is added to the sacrificial capping layer during the implant process.

A method for fabricating a semiconductor device includes forming a low-k dielectric layer, forming a pattern by etching the low-k dielectric layer, and implanting a carbon-containing material into a surface of the pattern.

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.

An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face opposite to the first face, and including a p-type silicon carbide region in contact with the first face, a percentage of a first silicon atom among a plurality of silicon atoms present in a first layer as an uppermost layer being equal to or more than 90% and a site position of the first silicon atom being different from a site position of a silicon atom in a third layer from the first face and the same as a site position of a silicon atom in a fifth layer from the first face; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer including nitrogen.

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.