A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap enclosed in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.

The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.

Semiconductor device and fabrication method are provided. A plurality of spaced-apart fins is formed on a substrate. A dummy gate structure is formed across the fins over the substrate. A first interlayer dielectric layer is formed on the substrate and on a sidewall of the dummy gate structure, and a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than a top of the fins. A cut-out opening, according to a cut-out pattern, is formed through the dummy gate structure and between adjacent fins. A second interlayer dielectric layer is formed on the first interlayer dielectric layer and fills in the cut-out opening.

A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The method includes: forming a first material layer and a second material layer sequentially on a substrate; defining an active region of the semiconductor device on the substrate, the first material layer and the second material layer, wherein the active region includes a channel region; forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer; forming a first source/drain region and a second source/drain region on the substrate and the second material layer respectively; and forming a gate stack around the outer periphery of the channel region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack formed over the substrate. The semiconductor device structure includes a spacer structure formed over a sidewall of the gate stack. The spacer structure includes a dielectric layer, a silicon rich layer, and a protection layer. The dielectric layer is formed between the gate stack and the silicon rich layer. The silicon rich layer is formed between the dielectric layer and the protection layer. A first atomic percentage of silicon in the silicon rich layer is greater than about 50%. The semiconductor device structure includes a source/drain structure formed over the substrate. The spacer structure is formed between the source/drain structure and the gate stack.