A method of processing a wafer having a plurality of devices formed in respective areas on a face side of the wafer, the areas being demarcated by a plurality of intersecting projected dicing lines, includes a low-viscosity resin applying step of coating the face side of the wafer with a first liquid resin of low viscosity to cover an area of the wafer where the plurality of devices are present, a high-viscosity resin applying step of, after the low-viscosity resin applying step, coating the face side of the wafer with a second liquid resin of higher viscosity than the first liquid resin in overlapping relation to the first liquid resin, a resin curing step of curing the first liquid resin and the second liquid resin that have coated the face side of the wafer into a protective film, and a planarizing step of planarizing the protective film.

A method of processing a wafer having a plurality of devices formed in respective areas on a face side of the wafer, the areas being demarcated by a plurality of intersecting projected dicing lines, includes a resin applying step of coating the face side of the wafer with a liquid resin to cover an area of the wafer where the plurality of devices are present, a resin curing step of curing the liquid resin into a protective film, a protective tape laying step of laying a protective tape on an upper surface of the protective film, and a planarizing step of planarizing a face side of the protective tape.

Provided is a new cerium-based particle and a polishing slurry composition including the same. The new cerium-based particle may include a self-assembly of fine particles and an organic material.

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

A semiconductor structure is provided. The semiconductor structure includes a base substrate including a plurality of non-device regions; a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions; a first barrier layer on sidewalls of the edge fin; and an isolation layer on the base substrate. The isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure. The isolation layer further has a material density smaller than the first barrier layer.

A slurry containing abrasive grains, a liquid medium, and a salt of a compound represented by formula (1) below, in which the abrasive grains include first particles and second particles in contact with the first particles, the first particles contain cerium oxide, and the second particles contain a hydroxide of a tetravalent metal element. ##STR00001##
[In formula (1), R represents a hydroxyl group or a monovalent organic group].

Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Provided is a package structure includes a first die, a first dielectric layer, a second dielectric layer and a carrier. The first dielectric layer covers a bottom surface of the first die. The first dielectric layer includes a first edge portion and a first center portion in contact with the bottom surface of the first die. The second dielectric layer is disposed on the first dielectric layer and laterally surrounding the first die. The second dielectric layer includes a second edge portion and a second center portion. The second edge portion is located on the first edge portion, and the second edge portion is thinner than the second center portion. The carrier is bonded to the first dielectric layer through a bonding film.

A semiconductor device includes a core insulating layer extending in a first direction, an etch stop layer disposed on the core insulating layer, a channel layer extending along a sidewall of the core insulating layer and a sidewall of the etch stop layer, conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction, and an impurity region formed in an upper end of the channel layer.