Implementations of a semiconductor substrate may include a plurality of die including at least one contact; and a plurality of portions of an encapsulant on a surface of the semiconductor substrate, wherein each portion of the plurality of portions extends immediately above a plane of the at least one contact.

A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.

The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor pattern structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

An imprint apparatus cures an imprint material supplied onto a substrate held by a substrate holder by bringing a mold held by a mold holder into contact with the imprint material. The imprint apparatus includes an adjuster to adjust a distance between the substrate holder and the mold holder for contact and separation between the imprint material and the mold, an energy supply tool to supply, to the imprint material, energy for curing the imprint material supplied onto the substrate held by the substrate holder, and a controller to control the adjuster and the energy supply tool. The controller controls the adjuster so as to start separation between the imprint material and the mold in a period during which the energy supply tool supplies the energy to the imprint material that is in contact with the mold.

Disclosed are an isolation structure of a photoresist stripper, a TFT array, and preparation methods thereof. The isolation structure includes a protective layer and a hardened layer arranged on the protective layer. The hardened layer is formed by plasma bombarding the protective layer with gas(es) and is configured to insulate the photoresist stripper. By forming the hardened layer on the surface of the protective layer including the organic planar layer, the hardened layer can prevent chemical agents (such as photoresist stripper) adopted in the subsequent process from getting into the protective layer, so as to keep the photoresist stripper from the protective layer, protecting the protective layer.

A mask material for plasma dicing, which is used in a plasma step, whose surface roughness Rz at the surface side that does not touch with an adherend is from 0.1 μm to 1.5 μm; a mask-integrated surface protective tape; and a method of producing a semiconductor chip.

[Subject] There is provided a gap filling composition which can reduce pattern collapse and a pattern forming method using the composition. [Solution means] There is provided a gap filling composition including a polymer having a certain structure and an organic solvent. There is provided a pattern forming method using a certain polymer.

A method of manufacturing a semiconductor device, the method including: a first film deposition process of stacking a polymer film on a substrate on which a recess is formed, wherein the polymer film is a film of a polymer having a urea bond and is formed by polymerizing a plurality of kinds of monomers; a second film deposition process of stacking a sealing film on the substrate in a state in which at least a bottom and a sidewall of the recess are covered with the polymer film; and a desorbing process of desorbing and diffusing the polymer film under the sealing film through the sealing film by depolymerizing the polymer film by heating the substrate to a first temperature.

The present disclosure provides a vertical memory structure with air gaps and a method for preparing the vertical memory structure. The vertical memory structure includes a semiconductor stack including a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.