Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10 and about 50.

An apparatus comprising a memory array comprising wordlines, digit lines, and memory cells, with each memory cell coupled to an associated wordline and an associated digit line. Each memory cell comprises a monocrystalline silicon material adjacent to an access device, a monocrystalline metal silicide material directly contacting the monocrystalline semiconductor material, a metal material directly contacting the monocrystalline metal silicide material, and a storage device adjacent to the metal material. Electronic devices, electronic systems, and methods of forming an electronic device are also disclosed.

A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.

Disclosed are a method for monitoring generation of a nickel metal silicide, comprising the steps: step 1, sequentially forming a first dielectric layer and a second polysilicon layer on the surface of a test silicon wafer; step 2, forming a nickel-platinum alloy on the surface of the second polysilicon layer; step 3, performing first annealing process to form a first nickel metal silicide having a molecular formula of Ni.sub.2Si; step 4, removing the unreacted nickel-platinum alloy remaining on the surface of the nickel metal silicide; and step 5, measuring the square resistance of the first nickel metal silicide to monitor the first annealing process. The stability and reliability of the monitoring result can be improved and misjudgment can be prevented.

A titanium silicide region forming method includes: performing a pretreatment to expose a clean surface of a silicon layer of a workpiece; forming a titanium-containing region and a titanium silicide region on the silicon layer after performing the pretreatment; and supplying a fluorine-containing gas to the workpiece including the titanium-containing region and the titanium silicide region so as to selectively etch the titanium-containing region with respect to the titanium silicide region.

A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.

An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.

An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.