A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.

A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

Provided is a method of forming an amorphous silicon layer. The method includes depositing an amorphous silicon layer on a substrate in a chamber; performing a post-treatment on an upper surface portion of the amorphous silicon layer using plasma by activating a post-treatment gas containing at least one component of nitrogen and oxygen groups, in order to improve the etch rate and surface roughness of the amorphous silicon layer; providing a purge gas to the chamber; and evacuating the chamber using a pump.

A semiconductor device according to an embodiment includes a SiC layer, a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, a first region provided between the SiC layer and the gate insulating film, and a second region provided in the SiC layer. The first region contains at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine). The second region provided adjacent to the first region, and the second region has a higher oxygen concentration than a concentration of the at least one element.

A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.

Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature. The methods may include forming plasma effluents of the silicon-containing precursor and depositing a silicon-containing material on the substrate. The methods may include providing a hydrogen-containing precursor to the processing region, forming plasma effluents of the hydrogen-containing precursor, and etching the silicon-containing material from a sidewall of the feature.

The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.