A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

Provided is a substrate processing method of filling a recess of a predetermined uneven pattern formed on a substrate with a film forming material by performing a first film forming processing, a first etching processing and a second film forming processing on the substrate, using a vertical substrate processing apparatus and a control apparatus controlling operations of the vertical substrate processing apparatus. The method includes calculating a first film forming condition, a first etching condition, and a second film forming condition by the control apparatus such that the film forming material is filled in the recess without any void after the second film forming processing; and performing the first film forming processing, the first etching processing and the second film forming processing on the substrate based on the calculated first film forming condition, first etching condition and second film forming condition.

A dielectric layer is formed on a silicon substrate. A liner layer is formed on the dielectric layer. A conductive metal layer is formed on the liner layer. A first sputter etching operation is performed on the conductive metal layer, wherein the first sputter etching operation uses a first type of etch chemistry configured to subtractively pattern the conductive metal layer for a first etching time period resulting in the remaining conductive metal layer having respective sidewalls that are not substantially vertical. A second sputter etching operation is performed on the remaining conductive metal layer, wherein the second sputter etching operation uses a second type of etch chemistry configured to further subtractively pattern the remaining conductive metal layer for a second etching time period resulting in the remaining conductive metal layer having respective sidewalls that are substantially vertical. The conductive metal layer remaining after the second sputter etching operation comprises a metal interconnect.

A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N.sub.2 gas and H.sub.2 gas and is performed at a temperature that is at least 300° C.

A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.

Various embodiments herein relate to methods and apparatus for electroplating cobalt on a substrate. In many cases, the cobalt is electroplated into recessed features. The recessed features may include a seed layer such as a cobalt seed layer. Electroplating may occur through a bottom-up mechanism. The bottom-up mechanism may be achieved by using particular additives (e.g., accelerator and suppressor), which may be present in the electrolyte at particular concentrations. Further, leveler, wetting agent, and/or brightening agents may be used to promote high quality plating results. In various embodiments, the substrate is pre-treated to remove oxide (and in some cases carbon impurities) from the seed layer before electroplating takes place. Further, the electrolyte may have a particular conductivity to promote uniform plating results across the face of the substrate.

A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.

The present application discloses a semiconductor device with a landing pad of conductive polymer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a landing pad of conductive polymer disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a conductive polymer layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The landing pad of conductive polymer comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.