Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.

One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

Various embodiments herein relate to methods and apparatus for electroplating cobalt on a substrate. In many cases, the cobalt is electroplated into recessed features. The recessed features may include a seed layer such as a cobalt seed layer. Electroplating may occur through a bottom-up mechanism. The bottom-up mechanism may be achieved by using particular additives (e.g., accelerator and suppressor), which may be present in the electrolyte at particular concentrations. Further, leveler, wetting agent, and/or brightening agents may be used to promote high quality plating results. In various embodiments, the substrate is pre-treated to remove oxide (and in some cases carbon impurities) from the seed layer before electroplating takes place. Further, the electrolyte may have a particular conductivity to promote uniform plating results across the face of the substrate.

A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top potion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.

Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. Methods may also involve using a remote plasma source to generate the nitrogen-based plasma. Methods also involve annealing the substrate.

Methods for depositing a metal film on a doped amorphous silicon layer as a nucleation layer and/or a glue layer on a substrate. Some embodiments further comprise the incorporation of a glue layer to increase the ability of the doped amorphous silicon layer and metal layer to stick to the substrate.

Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.

A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.

A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 μm to 100 μm. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius.

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.