Methods and apparatus that forms a stabilization layer on copper-based material to inhibit formation of copper voids in the copper-based material. In some embodiments, a method of forming the stabilization layer on the copper-based material includes depositing a first stabilization layer on the copper-based material where the first stabilization layer forms a continuous film on the copper-based material and is formed of a first material that does not alloy with copper, depositing a second stabilization layer on the first stabilization layer where the second stabilization layer is formed from a second material that alloys with copper and where the first stabilization layer is configured to inhibit formation of voids in the copper-based material during subsequent high thermal budget processing.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a buffer layer, at least one recess, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The buffer layer is present between the semiconductor substrate and the dielectric layer. The recess extends into the semiconductor substrate through the dielectric layer and the buffer layer, in which the buffer layer has a removing rate with respect to an etching process for forming the recess. The removing rate of the buffer layer is between those of the semiconductor substrate and the dielectric layer. The conductor is present in the recess.

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

In one embodiment of the present disclosure, a method for electrochemical deposition on a workpiece includes (a) obtaining a workpiece including a feature; (b) depositing a first conductive layer in the feature; (c) moving the workpiece to an integrated electrochemical deposition plating tool configured for hydrogen radical H* surface treatment and electrochemical deposition; (d) treating the first conductive layer using a hydrogen radical H* surface treatment in a treatment chamber of the plating tool to produce a treated first conductive layer; and (e) maintaining the workpiece in the same plating tool and depositing a second conductive layer in the feature on the treated first conductive layer in an electrochemical deposition chamber of the plating tool.

A method for forming a semiconductor structure includes forming a dielectric layer with an opening on a substrate; forming a material film in the opening; forming a blocking film on the material film; and removing the blocking film at the bottom of the opening to expose the material film. The remaining blocking film forms an initial blocking layer. The method further includes forming a conductive-material film in the opening; performing an annealing process to form a contact layer at the bottom of the opening by making the substrate, the material film, and the conductive-material film react with each other; and planarizing the conductive-material film, the initial blocking layer, and the material film to expose the dielectric layer. The remaining initial blocking layer forms a blocking layer in the opening; and the remaining conductive-material film forms a plug in contact with the blocking layer and the contact layer.

To provide a film forming material and a film forming process for forming, at a lower temperature, a Ge-containing Co film including a desired amount of Ge. A film forming material for forming a Ge-containing Co film according to the invention is represented by either formula (1) or formula (2) below R.sup.1R.sup.2R.sup.3Ge—Co(CO).sub.4 (1) (where R.sup.1, R.sup.2 and R.sup.3 are each independently hydrogen, a nonaromatic hydrocarbon group, a halogeno group or a halogenated nonaromatic hydrocarbon group; however, the nonaromatic hydrocarbon group excludes a crosslinked nonaromatic hydrocarbon group, and the halogenated nonaromatic hydrocarbon group excludes a crosslinked halogenated nonaromatic hydrocarbon group) Co(CO).sub.4R.sup.4R.sup.5Ge—Co(CO).sub.4 (2) (where R.sup.4 and R.sup.5 are each independently hydrogen, a nonaromatic hydrocarbon group, a halogeno group or a halogenated nonaromatic hydrocarbon group; however, the nonaromatic hydrocarbon group excludes a crosslinked nonaromatic hydrocarbon group, and the halogenated nonaromatic hydrocarbon group excludes a crosslinked halogenated nonaromatic hydrocarbon group).

Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.

A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

The present application discloses a semiconductor device with adjustment layers and a method for fabricating the semiconductor device with the adjustment layers. The semiconductor device includes a substrate, an interconnection structure positioned on the substrate, a contact positioned penetrating the interconnection structure, and two adjustment layers positioned on sidewalls of the contact.