Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.

Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

A method of fabricating a semiconductor device includes forming at least one fin on a substrate, a plurality of dummy gates over the at least one fin, and a sidewall spacer on the dummy gates. Source and drain regions are epitaxially formed contacting the at least one fin and laterally adjacent the dummy gates, where forming the source and drain regions leaves a void below the source and drain regions and adjacent the dummy gates. The dummy gates are replaced with active gates, each having a gate dielectric on the sidewall spacer and a gate electrode on the gate dielectric. A patterned layer is formed exposing a selected active gate of the active gates. A first etch is performed to remove exposed portions of the gate electrode of the selected active gate. A second etch is performed, after the first etch, to remove exposed portions of a gate dielectric of the selected active gate.

A semiconductor device includes a substrate including a first active pattern and a second active pattern, a gate electrode including a first gate electrode on the first active pattern and a second gate electrode on the second active pattern, a gate cutting pattern between the first and second gate electrodes, gate spacers on opposing side surfaces of the gate electrode, and a gate capping pattern on top surfaces of the gate electrode, the gate cutting pattern, and the gate spacers and extending in the first direction. The gate cutting pattern includes a first and second side surfaces, which are opposite to each other in a second direction crossing the first direction. The first and side surfaces are in contact with respective ones of the gate spacers, and the top surface of the gate cutting pattern is closer to the substrate than the top surfaces of the pair of gate spacers.

A method of forming a semiconductor device structure is provided. The method includes forming semiconductor fins at a first conductivity type region and a second conductivity type region of a substrate, forming a sacrificial gate structure across a portion of the semiconductor fins, wherein the sacrificial gate structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer over the sacrificial gate dielectric layer, and the sacrificial gate dielectric layer on the semiconductor fins of the first conductivity type region is asymmetrical in thickness between a top and a sidewall of the semiconductor fins. The method also includes forming a gate spacer on opposite sidewalls of the sacrificial gate structure, recessing the semiconductor fins not covered by the sacrificial gate structure and the gate spacer, forming source/drain feature on the recessed semiconductor fins, and removing the sacrificial gate structure to expose the top of the semiconductor fins.

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a recess between gate spacers of the gate structure by recessing the gate structure below upper surfaces of the gate spacers; depositing a first layer of a dielectric material in the recess along sidewalls and a bottom of the recess; after depositing the first layer, performing a first etching process to remove portions of the first layer of the dielectric material; and after the first etching process, depositing a second layer of the dielectric material in the recess over the first layer of the dielectric material.

The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F.sub.2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes a gate spacer on a sidewall of the gate structure. The semiconductor structure also includes a source/drain feature adjacent to the gate structure. The semiconductor structure also includes a doped region extending along a bottom surface of the gate spacer. The source/drain feature has a curved sidewall connecting a top surface of the doped region and a bottom surface of the doped region.

Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.