Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth. The doped region can suppress the induced doped region around the second doped region, so that the parasitic capacitance of the open-base bipolar transistor is reduced and the response speed is improved.

A semiconductor device, including a semiconductor substrate, a transistor section and a diode section arranged in a predetermined arrangement direction and provided on the semiconductor substrate, is provided. The diode section includes a drift region of a first conductivity-type provided in the semiconductor substrate, a base region of a second conductivity-type extending to a height of an upper surface of the semiconductor substrate and provided above the drift region, first cathode regions of the first conductivity-type, and second and third cathode regions of the second conductivity-type. The first, second, and third cathode regions extend to a height of a lower surface of the semiconductor substrate in a depth direction and provided below the drift region. The first and second cathode regions are provided in contact with each other, alternating in the arrangement direction, and sandwiched between the third cathode regions in an extension direction orthogonal to the arrangement direction.

A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor region between the first semiconductor region and the second electrode, a third semiconductor region between the first semiconductor region and the second electrode, a fourth semiconductor region between the first semiconductor region and the first electrode, a third electrode between the first electrode and the first semiconductor region, a first insulating film between the third electrode and both the first electrode and the first semiconductor region, a fifth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, a sixth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, and a seventh semiconductor region between the fourth semiconductor region and the first insulating film and in contact with the first semiconductor region.

A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region is connected neither to the collector electrode nor to the emitter electrode. The bipolar transistor has unusually high emitter-to-base and emitter-to-collector reverse breakdown voltages. In the case of a PNP-type RBJT, an N base region extends into a P epitaxial layer, and a plurality of P++ collector regions extend into the base region. Each collector region is annular, and rings a corresponding diode cathode region. Parts of the epitaxial layer serve as the emitter, and other parts serve as the diode anode. Insulation features separate metal of the collector electrode from the base region, and from P type silicon of the epitaxial layer, so that the diode cathode is separated from the base region. This separation prevents base current leakage and reduces power dissipation during steady state on operation.

A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor region between the first semiconductor region and the second electrode, a third semiconductor region between the first semiconductor region and the second electrode, a fourth semiconductor region between the first semiconductor region and the first electrode, a third electrode between the first electrode and the first semiconductor region, a first insulating film between the third electrode and both the first electrode and the first semiconductor region, a fifth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, a sixth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, and a seventh semiconductor region between the fourth semiconductor region and the first insulating film and in contact with the first semiconductor region.

A semiconductor device includes a multilayer structure including an n i layer, a p anode layer formed on the front surface of the n i layer, an n buffer layer formed on the back surface of the n i layer, an n+ cathode layer and a p collector layer formed on the back surface of the n buffer layer or on the back surfaces of the n i layer and the n buffer layer such that the n+ cathode layer and the p collector layer are adjacent to each other in a plan view or adjacent portions thereof overlap each other in a plan view, a front surface electrode, and a back surface electrode. A vertical position in the multilayer structure of the n+ cathode layer in the multilayer structure differs from that of the p collector layer.

A power semiconductor device includes a semiconductor wafer, a thyristor structure, and a bipolar junction transistor. The thyristor structure includes a first emitter layer of a first conductivity type adjacent the first main side, a first base layer of a second conductivity type, a second base layer of the first conductivity type, a second emitter layer of the second conductivity type, a gate electrode, a first main electrode, and a second main electrode arranged. The bipolar junction transistor includes a base electrode electrically separated from the gate electrode, a third main electrode arranged on the first main side and a fourth main electrode arranged on the second main side. The first main electrode is electrically connected to the third main electrode and the second main electrode is electrically connected to the fourth main electrode.

A semiconductor device includes a multilayer structure including an n? i layer, a p anode layer formed on the front surface of the n? i layer, an n? buffer layer formed on the back surface of the n? i layer, an n+ cathode layer and a p collector layer formed on the back surface of the n? buffer layer or on the back surfaces of the n? i layer and the n? buffer layer such that the n+ cathode layer and the p collector layer are adjacent to each other in a plan view or adjacent portions thereof overlap each other in a plan view, a front surface electrode, and a back surface electrode. A vertical position in the multilayer structure of the n+ cathode layer in the multilayer structure differs from that of the p collector layer.

Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth. The doped region can suppress the induced doped region around the second doped region, so that the parasitic capacitance of the open-base bipolar transistor is reduced and the response speed is improved.

A semiconductor device, including a semiconductor substrate, a transistor section and a diode section arranged in a predetermined arrangement direction and provided on the semiconductor substrate, is provided. The diode section includes a drift region of a first conductivity-type provided in the semiconductor substrate, a base region of a second conductivity-type extending to a height of an upper surface of the semiconductor substrate and provided above the drift region, first cathode regions of the first conductivity-type, and second and third cathode regions of the second conductivity-type. The first, second, and third cathode regions extend to a height of a lower surface of the semiconductor substrate in a depth direction and provided below the drift region. The first and second cathode regions are provided in contact with each other, alternating in the arrangement direction, and sandwiched between the third cathode regions in an extension direction orthogonal to the arrangement direction.