A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.

Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Semiconductor structures are provided. Each of the transistors includes a first source/drain region over a semiconductor fin extending in a first direction, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction perpendicular to the first direction. In a first transistor of the transistors, a first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors, A second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate extending in the second direction. A first contact of the first source/drain region is narrower than a second contact of the second source/drain region along the first direction.

The disclosure provides integrated circuit (IC) layouts and methods to form the same. An IC layout may include two standard cells, with a well contact cell laterally between them. The well contact cell may include a single semiconductor region having the first doping type, an active bridge region within the single semiconductor region, extending continuously from the first active region of the first standard cell to the third active region of the second standard cell. A doped tap region within the single semiconductor region is laterally separated from the active bridge region. The doped tap region is laterally aligned with the second active region and the fourth active region.

Semiconductor structures are provided. Each transistor includes a first source/drain region over a semiconductor fin, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction. In a first transistor of the transistors, the first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors. The second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate. A first contact of the first source/drain region is separated from a spacer of the metal gate electrode of the first transistor. A second contact of the second source/drain region is in contact with a spacer of the dielectric-base dummy gate.

A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.