The present invention introduces a new shielded gate trench SBR (Super Barrier Rectifier) wherein an epitaxial layer having special MSE (multiple stepped epitaxial) layers with different doping concentrations decreasing in a direction from a substrate to a top surface of the epitaxial layer, wherein each of the MSE layers has an uniform doping concentration as grown. Forward voltage V.sub.f is significantly reduced with the special MSE layers. An integrated circuit comprising a SGT MOSFET and a SBR formed on a single chip obtains benefits of low on-resistance, low reverse recovery time and high avalanche capability from the special MSE layers.

A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

A body diode is energized by inputting a BD energization pulse signal having a predetermined cycle. At the start of energization of the body diode and immediately before termination thereof, an ON signal of a Von measurement pulse signal is input to a high-temperature semiconductor chip at a timing different from that of an ON signal of the BD energization pulse signal, thereby passing a drain-source current through a MOSFET, and a drain-source voltage is measured. Thereafter, energization of the body diode is terminated. At room temperature before and after the energization of the body diode, the drain-source voltage is measured by inputting the ON signal of the Von measurement pulse signal. A semiconductor chip for which a fluctuation amount of the drain-source voltage at a high temperature and a fluctuation amount of the drain-source voltage at room temperature are within predetermined ranges is determined to be a conforming product.

The present application discloses a super junction device, which includes: an N-type redundant epitaxial layer and an N-type buffer layer sequentially formed on an N-type semiconductor substrate; a trench filled super junction structure is formed on the N-type buffer layer; a back structure includes a drain region and a patterned back P-type impurity region; the N-type semiconductor substrate is removed in a back thinning process, and the N-type redundant epitaxial layer is completely or partially removed in the back thinning process; the resistivity of the N-type semiconductor substrate is 0.1-10 times the resistivity of a top epitaxial layer, the resistivity of the N-type redundant epitaxial layer is 0.1-10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The present application further discloses a method for manufacturing a super junction device.

A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

A vertical field effect transistor. The vertical field effect transistor includes: a drift area including a first conductivity type; a semiconductor fin on or above the drift area, a source/drain electrode on or above the drift area; and a shielding structure, which is situated laterally adjacent to the at least one side wall of the semiconductor fin in the drift area, the shielding structure including a second conductivity type, which differs from the first conductivity type, and the semiconductor fin being electrically conductively connected to the source/drain electrode.

A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

A semiconductor device includes a semiconductor substrate, a contact region, a carrier suppression region and an electrode. The semiconductor substrate is shared by an insulated gate bipolar transistor (IGBT) region with an IGBT element and a freewheeling diode (FWD) region with an FWD element. The carrier suppression region is exposed from a surface of the semiconductor substrate in the IGBT region, and has a lower impurity concentration than the contact region. The carrier suppression region has a Schottky barrier junction with the electrode.

A semiconductor device includes: a chip having a main surface; a first conductive type first region formed on a surface layer portion of the main surface; a second conductive type second region formed on a surface layer portion of the first region; a drain region formed on a surface layer portion of the second region; a source region formed on the surface layer portion of the first region at a distance from the second region; and a second conductive type floating region formed in the first region at a thickness position between a bottom portion of the first region and a bottom portion of the second region and being spaced apart from the bottom portion of the second region, wherein the floating region faces the second region with a portion of the first region interposed between the floating region and the second region.