According to an embodiment, a transistor device includes a semiconductor body. The semiconductor body has a first surface, a second surface opposing the first surface, side faces, an active area, an edge termination region that laterally surrounds the active area, a drain region of a first conductivity type at the second surface, a drift region of the first conductivity type on the drain region, and a body region of a second conductivity type that opposes the first conductivity type on the drift region. In the active area, a source region of the first conductivity type is arranged on the body region. The body region has a doping concentration that is higher in the active area than in the edge termination region.

A transistor device includes: a semiconductor body having opposing first and second surfaces; an edge termination region laterally surrounding an active area; a drain region of a first conductivity type at the second surface; and a drift region of the first conductivity type on the drain region. In the active area, a body region of a second conductivity type is on the drift region, a source region of the first conductivity type is on the body region, and at least one gate electrode is positioned in a gate trench that extends into the semiconductor body from the first surface. A superjunction structure includes columns of the second conductivity type extending into the semiconductor body substantially perpendicular to the first surface in the active area and edge termination region. A first contact extends through the body region for each second conductivity type column in the active region and is electrically conductive.

An IGBT device and a method for manufacturing it, the device includes a super junction structure that has several N-type pillars and P-type pillars arranged alternately; a cell unit that is located in an N-type epitaxial layer, and the N-type epitaxial layer is located above the N-type substrate; each cell unit includes a trench gate, a P-type body region, and a source region; an N-type carrier injection layer, the N-type carrier injection layer is located in the N-type epitaxial layer, and the N-type carrier injection layer is spaced apart from the N-type substrate by the N-type epitaxial layer; the bottom of the P-type body region is located in the N-type carrier injection layer; and a collector region that is located at the bottom of the N-type substrate.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type; forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type; forming a plurality of trenches within the first III-nitride layer, wherein the plurality of trenches extend to a predetermined depth; epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type; forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions; epitaxially regrowing a III-nitride gate layer in the recess regions, wherein the III-nitride gate layer is coupled to the second III-nitride structure, and wherein the III-nitride gate layer is characterized by the second conductivity type.

A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.

Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate (101) of a first conductivity type, a drift region (102) of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions (103) of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures (104) arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer (1041) disposed on an inner surface of a trench and a conductive layer (1042) filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.

Variations of characteristics of a semiconductor device provided with a power MOSFET having a super junction structure are suppressed, and reliability of the semiconductor device is improved. A trench embedding an insulating film, which constitutes an insulator column therein, is formed in a first main surface of a semiconductor substrate whose crystal plane is a (110) plane. A crystal plane of a side surface of the trench in a short-side direction is a (111) plane, and a p-type diffusion layer constituting a p-column is formed in the above-mentioned side surface.

A semiconductor device is provided. A semiconductor device includes: a first semiconductor layer having an N-type conductivity; and a second semiconductor layer that is formed on the first semiconductor layer, wherein an active region is defined in the first semiconductor layer and the second semiconductor layer, the active region includes a plurality of first P pillars and a plurality of first N pillars alternately arranged along a first direction, in the active region, an upper pillar region including an upper region of the plurality of first P pillars and an upper region of the plurality of first N pillars, a lower pillar region including a lower region of the plurality of first P pillars and a lower region of the plurality of first N pillars, and a middle pillar region formed between the upper pillar region and the lower pillar region are defined, the entire charge amount of the upper pillar region is greater than the entire charge amount of the lower pillar region, and a P-type charge amount is greater than an N-type charge amount in the upper pillar region, while the N-type charge amount is greater than the P-charge amount in the lower pillar region.

Provided is a semiconductor device including a semiconductor chip which has a main surface, a high potential region which is formed in a surface layer portion of the main surface, a low potential region which is formed in the surface layer portion of the main surface at an interval from the high potential region, a first conductive type drift region which is formed in a region between the high potential region and the low potential region in the surface layer portion of the main surface, and a first conductive type resurf region which is formed partially in a surface layer portion of the drift region such as to expose a part of a region which serves as a current path in the drift region from the main surface and which has an impurity concentration higher than that of the drift region.

Provided is a semiconductor super junction power device which includes a super junction MOSFET cell array composed of multiple super junction MOSFET cells. A gate structure of the super junction MOSFET cell includes a gate dielectric layer, a gate and an n-type floating gate. The gate and the n-type floating gate are located above the gate dielectric layer; the gate is located on a side close to the n-type source region, and the n-type floating gate is located on a side close to the n-type drift region; the gate acts on the n-type floating gate through capacitive coupling. The n-type floating gate of at least one MOSFET cell is isolated from the p-type body region through the gate dielectric layer, and the n-type floating gate of at least one MOSFET cell contacts the p-type body region through an opening in the gate dielectric layer to form a p-n junction diode.