A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (μm). A width of the unit cell is one of less than and equal to 5.0 micrometers (μm). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.

A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a drift region (11) in the semiconductor body (100); a plurality of transistor cells (10); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells (10) includes: a first trench electrode (21) insulated from the semiconductor body (100) by a first dielectric layer (22); a second trench electrode (23) insulated from the semiconductor body (100) by a second dielectric layer (24); a source region (13) and a body region (14) in a first mesa region (111) between the first trench electrode (21) and the second trench electrode (23); and a compensation region (12), wherein the compensation region (12) adjoins the body region (14), the first dielectric (22), the second dielectric (24), and forms a pn-junction with the drift region (11), and wherein from the first trench electrode (21) and the second trench electrode (23) at least the first trench electrode (21) is connected to the gate node (G).

A drift layer is formed of silicon carbide and has a first conductivity type. A trench bottom protective layer is provided on a bottom portion of a gate trench and has a second conductivity type. A depletion suppressing layer is provided between a side surface of the gate trench and the drift layer, extends from a lower portion of a body region up to a position deeper than the bottom portion of the gate trench, has the first conductivity type, and has an impurity concentration of the first conductivity type higher than that of the drift layer. The impurity concentration of the first conductivity type of the depletion suppressing layer is reduced as the distance from the side surface of the gate trench becomes larger.

A semiconductor device includes a region of semiconductor material of a first conductivity type and having a first major surface. A body region of a second conductivity type opposite to the first conductivity type is in the region of semiconductor material. The body region includes a stripe region; a first segment in the stripe region and having a first peak dopant concentration, a first depth into the region of semiconductor material, and a first length along the first major surface; and a second segment in the stripe region laterally adjacent to the first segment, adjacent to the first major surface, and having a second peak dopant concentration, a second depth into the region of semiconductor material, and a second length along the first major surface. A source region of the first conductivity type is in the first segment but not in at least part of the second segment. An insulated gate electrode adjoins the first segment and is configured to provide a first channel region in the first segment, adjoins the second segment and configured to provide a second channel region in the second segment, and adjoins the first source region. A conductive structure is connected to the first segment, the second segment, and the source region. During a linear mode of operation, current flows first in the second segment but not in the first segment to reduce the likelihood of thermal runaway.

A semiconductor device includes an active gate metal structure disposed over a substrate, the active gate metal structure having a first sidewall and a second sidewall opposite to each other. The semiconductor device includes a first source/drain region disposed adjacent the first sidewall of the active gate metal structure with a first lateral distance. The semiconductor device includes a second source/drain region disposed adjacent the second sidewall of the active gate metal structure with a second lateral distance, wherein the second lateral distance is substantially greater than the first lateral distance. The semiconductor device includes a resist protective oxide (RPO) comprising a first portion extending over a portion of a major surface of the substrate that is laterally located between the second sidewall and the second source/drain region, wherein the RPO has no portion extending over a top surface of the active gate metal structure.

Embodiments are for vertical field effect transistors having different threshold voltages along the channel. A vertical fin having a vertical channel is formed, one end of the vertical channel including a doped layer, the doped layer causing a threshold voltage at the one end to be different from a remainder of the vertical channel. A source and a drain are formed each coupled to opposite ends of the vertical fin, gate material being formed on the vertical channel.

A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n.sup.−-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n.sup.−-type drain region and a gate electrode sandwich the n-type drift region in plan view.

Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.

A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.