A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10.sup.−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

A device includes a thinned semiconductor substrate having a first side and a second side opposite to the first side; and at least one radio frequency device at the first side, wherein the second side of the thinned semiconductor substrate is processed to reduce leakage currents or to improve a radio frequency linearity of the at least one radio frequency device through Bosch etching.

Method for making a transistor, comprising: making, on a substrate, a gate surrounded by a dielectric material; depositing a stop layer on the gate and the dielectric material; etching the stop layer in accordance with an active region pattern, forming a channel location located on the gate; etching the dielectric material located in the active region pattern, forming source and drain locations; depositing a semimetal material in the channel, source and drain locations; planarizing the semimetal material; crystallizing the semimetal material, forming the channel and the source and drain; and wherein the semimetal material of the channel is semiconductive and the semimetal material of the source and drain is electrically conductive.

A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

Provided is a semiconductor device, wherein at least one mesa portion contacting a gate trench portion thereof comprises: a first conductivity type emitter region with a doping concentration higher than a drift region, exposed on the top of the substrate and contacting the gate trench portion; a second conductivity type base region under the emitter region, contacting the trench portion, having a first peak in a doping concentration distribution in a depth direction of the substrate; a first conductivity type accumulation region under the base region, having a doping concentration higher than the drift region; and a second conductivity type intermediate region at a depth position between the base region and the accumulation region, having at least one of a second peak and a kink portion from the first peak to a depth position of a bottom of the trench portion in the doping concentration distribution in the depth direction.

A semiconductor device includes a contact opening extending through a source region and a body region of the device. An electrically insulative spacer lines sidewalls of the semiconductor substrate formed by the contact opening, and is recessed along the sidewalls such that at least part of the source region or body region is uncovered by the electrically insulative spacer. A body contact plug is in the contact opening. A first body contact region formed adjacent a bottom of the contact opening adjoins the body contact plug at the bottom of the contact opening. A second body contact region formed in the part of the source region or body region uncovered by the electrically insulative spacer adjoins the body contact plug along the part of the source region or body region uncovered by the electrically insulative spacer.

A super-junction IGBT device comprises a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed in a horizontal direction. Device cell structures are formed at tops of super-junction cells and each comprise a trench gate having a gate trench striding across an interface of the corresponding P-type pillar and the corresponding N-type pillar. A body region is formed at a top of the corresponding N-type pillar, and a source region is formed on a surface of the body region. The top of each N-type pillar is provided with one body region and two trench gates located on two sides of the body region, and each body region is isolated from the P-type pillars on the two sides of the body region through the corresponding trench gates. The invention further discloses a method for manufacturing a super-junction IGBT device. Self-isolation of the P-type pillars is realized, the on-state current capacity of the device is improved, and the on-state voltage drop of the device is reduced.

In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

Provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; a current sensing portion for detecting current flowing through the transistor portion; an emitter electrode set to an emitter potential of the transistor portion; a sense electrode electrically connected to the current sensing portion; and a Zener diode electrically connected between the emitter electrode and the sense electrode. Provided is a semiconductor device fabricating method including providing a transistor portion in a semiconductor substrate; providing a current sensing portion for detecting current flowing through the transistor portion; providing an emitter electrode set to an emitter potential of the transistor portion; providing a sense electrode electrically connected to the current sensing portion; and providing a Zener diode electrically connected between the emitter electrode and the sense electrode.