We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×10.sup.22 cm.sup.−3 or more, a SiO.sub.2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO.sub.2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO.sub.2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO.sub.2 layer and that has a carbon density of 1.0×10.sup.19 cm.sup.−3 or less.

A method of manufacturing a semiconductor integrated circuit includes forming a body region having a second conductivity type in an upper portion of a support layer having a first conductivity type and forming a well region having a second conductivity type in an upper portion of the support layer. An output side buried layer is formed inside the body region and a circuit side buried layer is formed inside the well region. A trench is dug to penetrate through the body region and a control electrode structure is buried in the gate trench. First and second terminal regions are formed on the well region and an output terminal region is formed on the body region. An output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.

A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.

In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.

A RC-IGBT with fast recovery integrated diode is proposed adopting the concept of a hybrid structure with conventional IGBT emitter trench-stop, separated from an embedded low efficiency injection anode diode. The body region of the IGBT and the anode region of the diode are separately patterned and doped, and the metal barrier layer is removed from the diode area allowing a direct ohmic contact of AlSi alloy on the underneath P-doped anode. A full-anode contact opening is present in the diode area. Moreover, corresponding dummy trenches in the diode area are short-circuited to the emitter electrode giving the benefit to reduce the transfer Miller capacitance. In this way, a good trade-off of VF vs Err can be obtained for the integrated diode without downgrading the IGBT performances both in terms of VCEsat and leakage, differently from the case of devices manufactured by lifetime control techniques.

An IGBT device and a method for manufacturing it, the device includes a super junction structure that has several N-type pillars and P-type pillars arranged alternately; a cell unit that is located in an N-type epitaxial layer, and the N-type epitaxial layer is located above the N-type substrate; each cell unit includes a trench gate, a P-type body region, and a source region; an N-type carrier injection layer, the N-type carrier injection layer is located in the N-type epitaxial layer, and the N-type carrier injection layer is spaced apart from the N-type substrate by the N-type epitaxial layer; the bottom of the P-type body region is located in the N-type carrier injection layer; and a collector region that is located at the bottom of the N-type substrate.

A vertical power semiconductor device includes a semiconductor body having opposing first and second main surfaces. At least part of a gate trench structure formed at the first main surface extends along a first lateral direction. Body and source regions directly adjoin the gate trench structure. A drift region is arranged between the body region and second main surface. A body contact structure includes first and second body contact sub-regions spaced at a first lateral distance along the first lateral direction. Each body contact sub-region directly adjoins the gate trench structure and has a larger doping concentration than the body region. In a channel region between the body contact sub-regions, the body contact structure has a second lateral distance to the gate trench structure along a second lateral direction perpendicular to the first lateral direction. The first lateral distance is equal to or less than twice the second lateral distance.

A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

A power semiconductor device includes a semiconductor substrate and a plurality of transistor cells formed in the semiconductor substrate and electrically connected in parallel to form a power transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the semiconductor substrate. The gate dielectric stack includes a ferroelectric insulator and a first dielectric insulator. The first dielectric insulator has a relative permittivity greater than that of silicon dioxide. A driver device for switching the power transistor and a corresponding method of operating the power transistor are also described.