Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first metal gate structure in a first dielectric layer. The method includes forming a second metal gate structure in the first dielectric layer, and the second metal gate structure includes a second metal electrode over a second gate dielectric layer. The method also includes forming a mask structure covering the first metal gate structure. The method includes etching a portion of the second gate dielectric layer and a portion of the second metal electrode of the second metal gate structure to form a first conductive portion extending above a top surface of the second gate dielectric layer. The method includes forming a metal layer over the first conductive portion, and the metal layer has a recess, and a top portion of the first conductive portion extends into the recess.

The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides of the semiconductor fin, a gate dielectric layer on a surface of the semiconductor fin above the isolation regions, and a gate on a part of the gate dielectric layer; and performing threshold voltage adjustment ion implantation on a part of the semiconductor fin that is not covered by the gate, so as to enable implanted impurities to diffuse into a part of the semiconductor fin that is covered by the gate. Forms of the present disclosure can reduce loss of impurities implanted by the threshold voltage adjustment ion implantation.

A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.

A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.

Disclosed is a semiconductor device. The semiconductor device includes: a substrate, including a first surface and a second surface opposite to each other; a gate, located on the first surface of the substrate; a source region located in the substrate on one side of the gate and a drain region located in the substrate another side of the gate; and an anti-punchthrough structure located in the substrate and including a third surface and a fourth surface opposite to each other. The third surface is adjacent to the first surface and lower than the first surface, and the anti-punchthrough structure is located between the source region and the drain region.

Method of making a transistor, comprising the following steps: make a gate and a first spacer on a first channel region of a first crystalline semiconducting layer; make first crystalline semiconductor portions on the second source and drain regions; make the second regions amorphous and dope them; recrystallise the second regions and activate the dopants present in the second regions; remove the first portions; make a second spacer thicker than the first spacer; make second doped crystalline semiconductor portions on the second regions, said second portions and the second regions of the first layer together form the source and drain of the transistor.

Characteristics of a semiconductor device are improved. The semiconductor device is configured to include an SOI substrate including an active region and an element isolation region (element isolation insulating film), a gate electrode formed in the active region via a gate insulating film, and a dummy gate electrode formed in the element isolation region. A dummy sidewall film is formed on both sides of the dummy gate electrode, and is arranged to match or overlap a boundary between the active region and the element isolation region (element isolation insulating film). According to such a configuration, a plug can be prevented from deeply reaching, for example, an insulating layer and a support substrate even when a contact hole is formed to be shifted.

Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first conductive region and a second conductive region. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region.

Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.

The present disclosure relates a method of manufacturing an integrated chip structure. The method forms an intermediate first material layer over a substrate and an intermediate second material layer on the intermediate first material layer. The intermediate second material layer is patterned to form an insulating layer. The intermediate first material layer is patterned to form a first material layer having an outermost sidewall indented inward from an outermost sidewall of the insulating layer. An ion bombardment process is performed on the insulating layer to dislodge one or more atoms from the insulating layer. A re-deposition process is performed to re-deposit the one or more atoms onto the outermost sidewall of the first material layer and to form a self-filling spacer below the insulating layer.