An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

The present disclosure relates to a semiconductor device, a solid-state imaging device, and a method for manufacturing a semiconductor device capable of improving the voltage dependency of a gate capacitance type.

Provided is a semiconductor device having a laminated structure in which a compound layer formed on a surface of a semiconductor layer and formed by the semiconductor layer reacting with metal, an insulating film layer in contact with the compound layer, and an electrode layer formed on the insulating film layer are laminated. The present technology can be applied, for example, to an analog-to-digital (AD) conversion part included in the solid-state imaging device.

A gate opening, a plurality of first openings arranged in a gate widthwise direction and having a reed shape, a second opening connecting the adjacent first openings, and a third opening connected to a side away from the arrangement of the first opening at an end of the arrangement are formed in an insulation layer. An ohmic cap layer is etched via the openings to form an asymmetric recess region.

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10.sup.−5-10.sup.−7 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10.sup.19 cm.sup.−3 and less than approximately 10.sup.−8 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 10.sup.20 cm.sup.−3.

A nitride semiconductor device 1 includes a first nitride semiconductor layer 13 that constitutes an electron transit layer, a second nitride semiconductor layer 14 that is formed on the first nitride semiconductor layer and that constitutes an electron supply layer, a semiconductor gate layer 15 that is disposed on the second nitride semiconductor layer and that has a ridge portion 15A at at-least a portion of the semiconductor gate layer and that includes an acceptor type impurity, a gate electrode 4 that is formed at least on the ridge portion of the semiconductor gate layer, a source electrode 3 and a drain electrode 5 that are disposed on the second nitride semiconductor layer, and a hole-pulling-out electrode 6 that is formed on the semiconductor gate layer in order to pull out holes existing in the semiconductor gate layer and that is electrically connected to the source electrode.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

[Object] To stably form a low-resistance electrical coupling between a metal and a semiconductor. [Solution] An electrical coupling structure includes: a semiconductor layer; a metal layer; and an intermediate layer that is held between the semiconductor layer and the metal layer, and includes an insulating layer provided on the semiconductor layer side and a two-dimensional material layer provided on the metal layer side.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10.sup.−5-10.sup.−7 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10.sup.19 cm.sup.−3 and less than approximately 10.sup.−8 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 10.sup.20 cm.sup.−3.