A method of manufacturing a semiconductor device includes forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate. A mask is formed on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer. The unmasked portion of the alloy semiconductor material layer not covered by the mask is irradiated with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer. The surface region surrounds the internal region.

A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.

On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.

A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate including a well region and an adjustment region over the well region. An isolation structure is disposed over the substrate and at least partially surrounds the well region and the adjustment region. An epitaxial layer is disposed over the adjustment region and surrounded by the isolation structure. A gate structure is disposed on the epitaxial layer. The present disclosure also provides a method for forming a semiconductor structure.

A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

A semiconductor device includes a substrate that includes peripheral and logic cell regions, a device isolation layer that defines a first active pattern on the peripheral region and second and third active patterns on the logic cell region, and first to third transistors on the first to third active patterns. Each of the first to third transistors includes a gate electrode, a gate spacer, a source pattern and a drain pattern. The second active pattern includes a semiconductor pattern that overlaps the gate electrode. At least a portion of a top surface of the device isolation layer is higher than a top surface of the second and third active patterns. A profile of the top surface of the device isolation layer includes two or more convex portions between the second and third active patterns.