An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.

A method of fabricating a laterally diffused metal oxide semiconductor transistor including providing a substrate, forming a first well of a first doping polarity type in the substrate, forming a gate on a portion of the first well, the gate including an oxide layer and an at least partially conductive layer on the oxide layer, and forming a mask on at least a portion of the gate and at least a portion of the first well, wherein the mask has a sloping edge. The method further includes forming a second well of a second doping polarity type at least partially in the first well by implanting ions in the first well, the second well extending under a portion of the gate, the second doping polarity type being of opposite type to the first doping polarity type. The method includes forming a first one of a source and drain of the first doping polarity type in or on the second well, thereby defining a channel of the transistor under the gate. The method further includes forming a second one of the source and drain of the first doping polarity type in or on the first well, wherein the implanting includes directing at least a first beam of ions towards the first well at an angle substantially perpendicular to a surface plane of the substrate, and directing at least a second beam of ions towards the first well at an angle substantially offset from a surface normal of the substrate.

The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

A network device includes one or more circuit components. The one or more circuit components include a semiconductor substrate, a first device terminal and a second device terminal, a drift region, and a mobility modulator. Both device terminals are coupled to the semiconductor substrate, the second device terminal being spatially separated from the first device terminal. The drift region is disposed on the semiconductor substrate between the first device terminal and the second device terminal, the drift region being configured to allow a flow of charge-carriers between the first device terminal and the second device terminal. The mobility modulator is coupled to the drift region, the mobility modulator being configured to selectively apply a field across the drift region responsive to one or more modulation signals, so as to modulate a mobility of charge-carriers as a function of longitudinal position along the drift region.

A semiconductor device includes: an n.sup.−-type epitaxial layer having an element main surface; a p.sup.−-type body region, an n.sup.+-type source region, and n.sup.+-type drain regions; and a gate electrode including a second opening and first openings formed in a portion separated from the second opening toward the drain regions, wherein the body region selectively has a second portion exposed to the first openings of the gate electrode, and wherein the semiconductor device further includes a p.sup.+-type body contact region formed in the portion of the body region exposed to the first openings and having an impurity concentration higher than an impurity concentration of the body region.

A semiconductor device is provided, which includes a substrate, a first and second doped wells, a drain and source regions, a gate structure, a field plate and a booster plate. The first and second doped wells are arranged in the substrate. The drain region is arranged in the first doped well and the source region is arranged in the second doped well. The gate structure is arranged over the substrate and between the source and drain regions. The field plate is arranged over the first doped well and the booster plate arranged between the field plate and the first doped well.

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.

Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a substrate, a source region and a drain region in the substrate, a buffer dielectric layer positioned on the substrate adjacent to the drain region, and a gate electrode laterally positioned between the source region and the drain region. The gate electrode includes a portion that overlaps with the buffer dielectric layer, and the portion of the gate electrode includes notches.