A method of fabricating an array substrate is provided. The method includes forming a plurality of first thin film transistors on a base substrate, a respective one of the plurality of first thin film transistors formed to include a first active layer, a first gate electrode, a first source electrode and a first drain electrode; and forming a plurality of second thin film transistors on the base substrate, a respective one of the plurality of second thin film transistors formed to include a second active layer, a second gate electrode, a second source electrode and a second drain electrode. Forming the first source electrode includes forming a first source sub-layer and forming a second source sub-layer in separate patterning steps. Forming the first drain electrode includes forming a first drain sub-layer and forming a second drain sub-layer in separate patterning steps.

A thin film transistor according to an embodiment includes a first semiconductor, a gate electrode overlapping the first semiconductor, a second semiconductor contacting a portion of the first semiconductor, and a source electrode and a drain electrode contacting the second semiconductor, the first semiconductor includes an oxide semiconductor, and the second semiconductor includes silicon.

An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a first thin film transistor located on the base substrate and including a first active layer; and a second thin film transistor located on the base substrate and including a second active layer; a matrix material of the first active layer is the same as that of the second active layer, and the first active layer and the second active layer satisfy at least one of the following conditions: a carrier mobility of the first active layer is greater than that of the second active layer, and a carrier concentration of the first active layer is greater than that of the second active layer. The array substrate is employed to compensate a difference in threshold voltage caused by a difference in channel width-to-length ratio of different thin film transistors.

Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.

A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices.

The present disclosure provides a thin-film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor of the present disclosure include a plurality of insulating layers, among which at least one insulating layer on the low temperature polysilicon layer comprises organic material, so vias could be formed in the organic material by an exposing and developing process, thereby effectively avoiding the over-etching problem of the low temperature polycrystalline silicon layer caused by dry etching process. By adopting the method for manufacturing the film transistors of the present disclosure, the contact area and uniformity of the drain electrode and the low temperature polysilicon material layer can be increased; the conductivity can be improved; and the production cycle of products can be greatly reduced and thereby improving the equipment capacity.

A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

A thin film transistor and a non-volatile memory device are provided. The thin film transistor comprises a gate electrode, and a metal oxide channel layer traversing the upper or lower portions of the gate electrode. The metal oxide channel layer has semiconductor properties while having bixbyite crystals. An insulating layer is disposed between the gate electrode and the metal oxide channel layer. Source and drain electrodes are electrically connected to both ends of the metal oxide channel layer, respectively.