This disclosure relates to the field of display technologies, and discloses a thin film transistor, a method for fabricating the same, a method for controlling the same, a display panel, and a display device. The thin film transistor includes: a base substrate, a semiconductor active layer on one side of the base substrate, a source electrically connected with one end of the semiconductor active layer, a drain electrically connected with the other end of the semiconductor active layer, a gate insulated from the semiconductor active layer, the source, and the drain, and a modulation electrode insulated from the semiconductor active layer, the gate, the source, and the drain. The modulation electrode is proximate to the drain, and an orthographic projection of the modulation electrode on the base substrate overlaps with an orthographic projection of the semiconductor active layer on the base substrate

A semiconductor device includes an active pattern on a substrate, source/drain patterns on the active pattern, a plurality of channel layers stacked on the active pattern to be vertically spaced apart from each other and connecting the source/drain patterns with each other, a gate electrode between the source/drain patterns to cross the active pattern and to surround the channel layers, and active contacts at opposite sides of the gate electrode to cover top surfaces of the source/drain patterns. A width of each of the active contacts is smaller than or equal to the largest width of each of the source/drain patterns. Each of the top surfaces of the source/drain patterns has an inclined surface that is inclined relative to a top surface of the substrate, and each of the active contacts includes a protruding portion that protrudes toward the inclined surface.

Some implementations described herein provide a semiconductor device that includes a first set of gate-all-around (GAA) structures, having a first gate pitch, that includes a first set of source/drains having a first source/drain width and a first set of top spacers, having a first spacer width, disposed between a first set of gates of the first set of GAA structures and the first set of source/drains. The semiconductor device includes a second set of GAA structures having a second gate pitch, that, includes a second set of source/drains having a second source/drain width and a second set of top spacers, having a second spacer width, disposed between a second set of gates of the second set of GAA structures and the second set of source/drains.

A method for manufacturing a display substrate is provided. The method includes: forming a first active layer arranged in the NMOS transistor region and a second active layer arranged in the PMOS transistor region on the base substrate; coating one side, facing away from the base substrate, of the first active layer and one side, facing away from the base substrate, of the second active layer with a first photoresist layer, forming a first pattern layer by patterning the first photoresist layer to expose at least two ends of the first active layer; forming N-type heavily doped regions by performing N-type heavy doping on the two ends of the first active layer with the first pattern layer as a mask; forming a second pattern layer by processing the first pattern layer to expose at least a middle region of the first active layer.

A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 .Math.m to about 2 .Math.m, and a length of the channel of the third transistor is in a range of about 1 .Math.m to about 2.5 .Math.m.

The present application relates to an active switch, a manufacturing method thereof and a display device. The manufacturing method of the active switch includes: sequentially forming a gate electrode, a gate insulating layer, an active layer, a semiconductor composite layer and a source electrode and a drain electrode on a substrate. The semiconductor composite layer includes a first N-type heavily doped amorphous silicon layer, a first N-type lightly doped amorphous silicon layer, a second N-type heavily doped amorphous silicon layer and a second N-type lightly doped amorphous silicon layer which are sequentially stacked, where the ion doping concentration of the first N-type heavily doped amorphous silicon layer is lower than that of the second N-type heavily doped amorphous silicon layer, and the ion doping concentration of the first N-type lightly doped amorphous silicon layer is higher than that of the second N-type lightly doped amorphous silicon layer.

A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f)selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a vertical stack of semiconductor channels, a source on a first side of the vertical stack of semiconductor channels, and a drain on a second side of the vertical stack of semiconductor channels, In an embodiment, a metal is below the source and in direct contact with the source, where a centerline of the metal is substantially aligned with a centerline of the source.