A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.

A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a lower portion and an upper portion over the lower portion. The lower portion and the semiconductor substrate have a first lattice mismatch. The upper portion and the semiconductor substrate have a second lattice mismatch different from the first lattice mismatch.

A semiconductor device includes a plurality of fins over a substrate. Each fin of the plurality of fins extends in a first direction substantially perpendicular to a bottom surface of the substrate, and each fin of the plurality of fins comprises a first doped region having a first dopant type. The semiconductor device further includes an isolation region over the substrate between a first fin of the plurality of fins and a second fin of the plurality of fins adjacent to the first fin. The semiconductor device further includes a second doped region extends continuously across the isolation region, the second doped region extends into each fin of the plurality of fins, and a dimension of the second doped region in the isolation region in a second direction perpendicular to the first direction is less than a dimension of the at least one isolation region in the second direction.

In some aspects, methods for forming a germanium thin film using a cyclical deposition process are provided. In some embodiments, the germanium thin film is formed on a substrate in a reaction chamber, and the process includes one or more deposition cycles of alternately and sequentially contacting the substrate with a vapor phase germanium precursor and a nitrogen reactant. In some embodiments, the process is repeated until a germanium thin film of desired thickness has been formed.

Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. By controlling the flow rate of various components of the plasma gas flow, plasmas exhibiting desired etching characteristics may be obtained. Such plasmas may be used in single or multistep etching operations, such as recess etching operations that may be used in the production of non-planar microelectronic devices.

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.