Transistor-based sensors and fabrication methods for a transistor-based sensor. A semiconductor layer is arranged over a substrate, and an interconnect structure is arranged over the semiconductor layer and the substrate. The semiconductor layer includes first sections composed of a semiconductor material, second sections composed of the semiconductor material, and cavities. The first sections have an alternating arrangement with the second sections in a lateral direction. The semiconductor material of the first sections is polycrystalline, and the semiconductor material of the second sections is single-crystal. First and second openings each extend in a vertical direction through the metallization levels of the interconnect structure to the semiconductor layer or through the substrate to the semiconductor layer. The first opening defines a first fluid inlet coupled to the cavities, and the second opening defines a first fluid outlet coupled to the cavities.

Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and patterning the germanium containing layer stopping on the crystalline oxide layer to form a base region. The method may further include forming emitter and collector extension regions on opposing sides of the base region using ion implantation, and epitaxially forming an emitter region and collector region on the crystalline oxide layer into contact with the emitter and collector extension regions. The crystalline oxide layer provides a seed layer for the epitaxial formation of the emitter and collector regions.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor. The capacitor additionally comprises a polar layer comprising a base polar material doped with a dopant, wherein the base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The semiconductor device additionally comprises a lower barrier layer comprising a refractory metal or an intermetallic compound between the lower conductive oxide electrode and the conductive via.

A heterojunction bipolar transistor (HBT) is fabricated using a selectively implanted collector (SIC) implant mask including multiple openings located over the HBT's collector region. During the SIC implant process, resist mask edge (well proximity) effects caused by the SIC dopant passing through the multiple openings generates multiple secondary shallow increased-doping regions in the collector region adjacent to the substrate surface, where the mask openings are sized such that each secondary increased-doping region has a doping concentration that is comparable to primary increased-doping regions, which are simultaneously formed deeper in the SIC region. A base structure and an emitter structure are then formed over the SIC region using known techniques. The secondary increased-doping regions produce enhanced base-collector junction between the SIC region and the base structure that measurably decreases Kirk Effect by way of enhancing the HBT's cutoff frequency (Ft) and break-down voltage (BV.sub.CEO).

This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.