The present application provides methods for manufacturing BiCMOS device and the heterojunction bipolar transistor (HBT) contained therein. In formation of a raised extrinsic base region of the heterojunction bipolar transistor, the epitaxial silicon is doped with carbon (C) and boron (B) in situ and is doped with a metal catalyst simultaneously, then, the plasma treatment and the laser annealing are conducted to the carbon, and a graphene region is formed in the Si epitaxial layer. Because of high conductivity of graphene, the base resistance of the SiGe HBT can be reduced to enhance its radiation performance. The above method can be applied to conventional BiCMOS device process by performing plasma treatment and laser annealing to the doped carbon to form the graphene region in the extrinsic base region. The method is easily controlled and integrated into conventional BiCMOS device process.

The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

A semiconductor device includes a first layer that contains gold (Au) and is formed on one surface of a semiconductor substrate and a second layer that contains nickel (Ni) and is formed on the first layer. The semiconductor device is provided with a via hole that passes through the second layer, the first layer, and the semiconductor substrate from one surface to another surface opposite thereto, and a via wiring is formed on the inner surface of the via hole. The second layer is a mask used when the semiconductor substrate is etched to form the via hole, and the first layer is a base layer for forming the second layer on the semiconductor substrate. By using an Au-containing layer as the first layer, side etching on the first layer is prevented when the semiconductor substrate is etched, and disconnection of the via wiring is prevented.

Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region that includes a converted dielectric. The converted dielectric is a dielectric material that has been converted to the dielectric from another material.

A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.

A method of manipulating deposition rates of poly-silicon and a method of manufacturing a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device are provided. The method of manipulating deposition rates of poly-silicon includes: providing a substrate, where a first surface of the substrate includes at least two of an oxide material region, a silicon nitride material region and a silicon material region; performing a first treatment on the first surface of the substrate, so as to manipulate the deposition rates of poly-silicon on different regions of the first surface to be closer; and forming a poly-silicon layer on the first surface of the substrate.

Methods of manufacturing a heterojunction bipolar transistor are described herein. An exemplary method can include providing a base/emitter stack, the base/emitter stack comprising a substrate, an etch stop layer over the substrate, an emitter contact layer over the etch stop layer, an emitter over the emitter contact layer, and/or a base over the emitter. The exemplary method further can include forming a collector. The exemplary method also can include wafer bonding the base to the collector. Other embodiments are also disclosed herein.

The disclosure provides a heterojunction bipolar transistor and a preparation method thereof. Since an emitter region has the same physical structure as a base region, and improves frequency characteristics of the device; Simultaneously with biaxial strain, uniaxial strain is introduced. Carrier transmission time in the collector region will be effectively reduced. By this structure, the width of the effective collector region is reduced, the collector junction capacitance is reduced, and the frequency characteristics of the device are further improved; an appropriate choice of the thickness of the Si cap layer can effectively reduce the accumulation of carriers at an interface and increase the gain of the device; at the same time, the preparation method of the bipolar transistor is completely compatible with a 90-nanometer CMOS process, which effectively reduces the development and manufacturing cost of the device.