In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2×10.sup.−11 A and the gate leak current is limited to less than 3.7×10.sup.−6 A/m.sup.2.

Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.

Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

A high voltage trench field plate power MOSFET device is fabricated in a substrate having first and second trenches separated from one another by a narrow epitaxial semiconductor drift pillar structure, where insulated gate electrode layers and insulated field plate layers are formed in the first and second trenches, and where a body well region is formed in an upper portion of the narrow epitaxial semiconductor drift pillar structure to include source contact regions in an active area, and to include an integrated ballast resistor section which connects one or more of the source contact regions to the termination area and which has no source contact regions.

An anti-fuse having two electrical connections is constructed by adding at least one zener diode and resistor to a power MOSFET. When the voltage across the two electrical connections exceeds the zener diode voltage and the maximum gate voltage of the MOSFET, the MOSFET burns out. This shorts out the device which can be used to bypass an LED or other load when that load burns out and forms an open circuit.

A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.

The disclosure relates to a semiconductor die, including a vertical power transistor device, a pull-down transistor device, and a capacitor. The pull-down transistor device is connected between a gate electrode of the vertical power transistor device and a ground terminal and connects the gate electrode to the ground terminal in a conducting state. The capacitor is connected between one of the load terminals of the vertical power transistor device and the control terminal of the pull-down transistor device and capacitively couples the one load terminal to the control terminal.

A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.

In an example, a semiconductor device includes an insulated gate transistor cell, a first region (e.g., a drain region and/or a drift region), a cathode region, a second region (e.g., an anode region and/or a separation region), and a source electrode. The insulated gate transistor cell includes a source region and a gate electrode. The source region and the cathode region are in a silicon carbide body. The gate electrode and the cathode region are electrically connected. The cathode region, the source region, and the first region have a first conductivity type. The second region has a second conductivity type and is between the cathode region and the first region. The source electrode and the source region are electrically connected. The source electrode and the second region are in contact with each other. A rectifying junction is electrically coupled between the source electrode and the cathode region.

An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop Vf.sub.D2 of the monolithic diode device is less than a forward voltage drop Vf.sub.D1 of the body diode of the MOSFET device. The forward voltage drop Vf.sub.D2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop Vf.sub.D2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.