A power path switch circuit includes: a power transistor unit including: a first vertical double-diffused metal oxide semiconductor (VDMOS) device, wherein a first current outflow end of the first VDMOS device is coupled to an output end of a power path; and a second VDMOS device, wherein a first current inflow end of the first VDMOS device and a second current inflow end of the second VDMOS device are coupled with a supply end of the power path; and a voltage locking circuit coupled to the first current outflow end and the second current outflow end, for locking a voltage at the second current outflow end to a voltage at the first current outflow end, so that there is a predetermined ratio between a first conductive current flowing through the first VDMOS device and a second conductive current flowing through the second VDMOS device.

A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

There are provided a transistor including a first semiconductor layer of a first conductivity type, a second semiconductor layer thereabove, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode facing the first impurity region and the second semiconductor layer with a gate insulating film interposed in between, and first and second main electrodes; a parasitic transistor with the second impurity region as a collector, the first and the second semiconductor layers as an emitter, and the first impurity region as a base; a parasitic diode with the first impurity region as an anode, and the first and the second semiconductor layers as a cathode; and a pn junction diode with the first impurity region as an anode, and the second impurity region as a cathode.

A semiconductor device includes a semiconductor body of a wide-bandgap semiconductor material. A plurality of first bond areas is connected to a first load terminal of the semiconductor device. First gate fingers are arranged between the first bond areas. The first gate fingers extend in a first lateral direction and branch off from at least one of a first gate line portion and a second gate line portion. Second gate fingers extend in the first lateral direction. A first length of any of the first gate fingers along the first lateral direction is greater than a second length of any of the second gate fingers along the first lateral direction. A sum of the first length and the second length is equal to or greater than a lateral distance between the first gate line portion and the second gate line portion along the first lateral direction.

A semiconductor apparatus has a silicon carbide substrate heavily doped with the first conductivity type and a lightly doped silicon carbide drift region of the first conductivity type over the silicon carbide substrate. A first body region in the drift region is doped with second conductivity type opposite the first. A first source region in the first body region is heavily doped with the first conductivity type. A gate trench is formed in the first source region and first body region. At least one sidewall of the gate trench is parallel to a crystal plane of the silicon carbide structure having greater carrier mobility than a C-face thereof. The gate trench extends a length of the first body region and the source region to a separation region laterally adjacent to the first region wherein the separation region is in the drift region.

In an embodiment, a semiconductor die includes a transistor device that has a cell field and an edge termination region, a source pad arranged on the cell field, a gate pad laterally arranged laterally adjacent the cell field and in the edge termination region, a shielding region laterally surrounding the cell field, the shielding region including a non-depletable doped. The polysilicon ESD protection diode is arranged laterally between the gate pad and the source pad and vertically above at least a portion of the shielding region, and includes at least two separate sections that are electrically coupled in parallel between the gate pad and the source pad. The sections are laterally spaced apart by a gap situated at a corner of the gate pad.

A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.

A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.