A power semiconductor die includes a substrate and a drift layer on the substrate. The drift layer includes an active area, an edge termination area surrounding the active area, and a thermal dissipation area surrounding the edge termination area. The thermal dissipation area is configured to reduce a thermal resistance of the power semiconductor die. By providing the thermal dissipation area, the operating voltage and/or current of the power semiconductor die can be increased without an increase in the active area. Further, the manufacturing yield of the power semiconductor die can be improved.

A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.

A semiconductor device includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the second conductivity type; a fifth semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration lower than an impurity concentration of the second semiconductor layer; a first electrode; and a second electrode. The fifth semiconductor region has one surface in contact with the first semiconductor region, another surface in contact with the third semiconductor region, and a side surface in contact with the gate insulating film.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer.

A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region overlying a shield region in an epitaxial or crystalline layer of the device. The polysilicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.

A SiC semiconductor device includes a main cell region and sense cell region being electrically isolated by an element isolation portion. The SiC semiconductor device includes a substrate, a first impurity region, a first current dispersion layer, first deep layers, a second current dispersion layer, a second deep layer, a base region, a trench gate structure, a second impurity region, first electrodes and a second electrode. The second impurity region, the first electrodes, and the second electrode are disposed at the main cell region and the sense cell region to form a vertical semiconductor element. The vertical semiconductor element allows a current flowing between the first electrode and the second electrode through a voltage applied to the gate electrode. The spacing interval between the deep layers at the element isolation portion is shorter than or equal to a spacing interval between the deep layers at the main cell region.

[Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same.

[Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.

A semiconductor device includes a transistor cell with a source region of a first conductivity type and a gate electrode. The source region is formed in a wide bandgap semiconductor portion. A diode chain includes a plurality of diode structures. The diode structures are formed in the wide bandgap semiconductor portion and electrically connected in series. Each diode structure includes a cathode region of the first conductivity type and an anode region of a complementary second conductivity type. A gate metallization is electrically connected with the gate electrode and with a first one of the anode regions in the diode chain. A source electrode structure is electrically connected with the source region and with a last one of the cathode regions in the diode chain.

The present disclosure can be applied to semiconductor devices and, in particular, relates to a MOSFET device made of silicon carbide and a method for manufacturing same. A metal-oxide film semiconductor field-effect transistor device of the present disclosure may comprise: a drain electrode; a substrate arranged on the drain electrode; an N-type drift layer arranged on the substrate; a current-spreading layer arranged on the drift layer; P-type well layers arranged on the current-spreading layer to define a channel; an N+ region arranged on the well layers; a damage prevention layer adjacent to the N+ region and having a lower N-type doping concentration than that of the N+ region; a P+ region arranged on one side of the channel; a gate oxide layer arranged on the current-spreading layer; a gate layer arranged on the gate oxide layer; and a source electrode arranged on the gate layer.