A vertical isolated gate FET transistor integrated in the front end of line of a semiconductor chip is disclosed. In one aspect, the transistor includes a modified version of a buried power rail and back side TSV (through semiconductor via) connection for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. In contrast to standard power rail/TSV combinations, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well includes a contact area adjacent the TSV. The TSV thereby acts as the gate of the transistor, while the rail and the contact area respectively act as source and drain or vice versa.

A semiconductor device includes a first external electrode with a first electrode surface portion; a second external electrode with a second electrode surface portion; a MOSFET chip with a built-in Zener diode which includes an active region and a peripheral region; a control IC chip which drives the MOSFET chip based on voltage or current between a drain electrode and a source electrode of the MOSFET chip; and a capacitor which supplies power to the MOSFET chip and the control IC chip. The first electrode surface portion is connected to either the drain electrode or the source, the second electrode surface portion is connected to either the source electrode or the drain electrode, a plurality of unit cells of the MOSFET with the built-in Zener diode are provided in the active region, and the breakdown voltage of the Zener diode is set to be lower than that of the peripheral region.

A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

A semiconductor structure includes a substrate; at least one mask layer spaced apart from the substrate in a first direction; a first semiconductor region of a first conductivity type between the substrate and the at least one mask layer; a second semiconductor region of a second conductivity type on the at least one mask layer; and a third semiconductor region of the first conductivity type on the first semiconductor region. The third semiconductor region may contact the second semiconductor region to form a PN-junction structure in a second direction different from the first direction. The semiconductor structure may be applied to vertical power devices and may be capable of increasing withstand voltage performance and lowering an on-resistance.

A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n.sup.+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p.sup.++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p.sup.+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

A vertical MOSFET having a trench gate structure includes an n.sup.-type drift layer and a p-type base layer formed by epitaxial growth. In the n.sup.-type drift layer, an n-type region, a first p.sup.+-type region, and a second p.sup.+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p.sup.+-type region is provided between the source electrode and the p-type base layer.

A semiconductor device includes a substrate, a semiconductor body and a metal layer between the substrate and the semiconductor body. The device further includes first and second electrodes, a first control electrode between the semiconductor body and the first electrode; and a second control electrode between the semiconductor body and the second electrode. The semiconductor body includes a first to fifth semiconductor layers. The second semiconductor layer is provided between the first semiconductor layer and the first electrode. The third semiconductor layer is selectively provided between the second semiconductor layer and the first electrode. The fourth semiconductor layer is provided between the first semiconductor layer and the second electrode. The fifth semiconductor layer selectively provided between the fourth semiconductor layer and the second electrode. The first, third and fifth semiconductor layers are of a first conductivity type. The second and fourth semiconductor layers are of a second conductivity type.

A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.

A vertical isolated gate FET transistor integrated in the front end of line of a semiconductor chip is disclosed. In one aspect, the transistor includes a modified version of a buried power rail and back side TSV (through semiconductor via) connection for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. In contrast to standard power rail/TSV combinations, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well includes a contact area adjacent the TSV. The TSV thereby acts as the gate of the transistor, while the rail and the contact area respectively act as source and drain or vice versa.

A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.