In a first vertical field-effect transistor in which first source regions and first connectors each of which electrically connects a first body region and a first source electrode are alternately and periodically disposed in a first direction (Y direction) in which a first trench extends, a ratio of LS [μm] to LB [μm] is at least 1/7 and at most 1/3, where LS denotes a length of one of the first source regions in the first direction, and LB denotes a length of one of the first connectors in the first direction, and LB≤−0.024×(VGS).sup.2+0.633×VGS−0.721 is satisfied for a voltage VGS [V] of a specification value of a semiconductor device, the voltage VGS being applied to a first gate conductor with reference to an electric potential of the first source electrode.

A silicon carbide semiconductor device has a termination region, which includes first to fourth semiconductor regions, one provided on the outer side of another. The second semiconductor region has first small regions that are provided in a region having an impurity concentration lower than that of the first semiconductor region, and have the same impurity concentration as first semiconductor region. The third semiconductor region has a lower impurity concentration than the first semiconductor region. The fourth semiconductor region has second small regions that have the same impurity concentration as the third semiconductor region. A width of the first semiconductor region is narrower than a width of the third semiconductor region.

A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material filling the insulation layer groove.

The present invention introduces a new shielded gate trench MOSFETs wherein epitaxial layer having special multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing in a direction from substrate to body regions, wherein each of the MSE layers has uniform doping concentration as grown. Specific on-resistance is significantly reduced with the special MSE structure. Moreover, in sore preferred embodiment, an MSO (multiple stepped oxide) structure is applied to the shielded gate structure to further reduce the specific on-resistance and enhance device ruggedness.

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

A power semiconductor device includes a semiconductor layer based on silicon carbide (SiC), a vertical drift region positioned to extend in a vertical direction inside the semiconductor layer and having a first conductive type, a well region positioned in at least one side of the vertical drift region to make contact with the vertical drift region and having a second conductive type, recess gate electrodes extending from a surface of the semiconductor layer into the semiconductor layer and buried in the vertical drift region and the well region to cross the vertical drift region and the well region in a first direction, source regions positioned in the well region between the recess gate electrodes and having the first conductive type, and insulating-layer protective regions surrounding lower portions of the recess gate electrodes, respectively, in the vertical drift region, and having the second conductive type.

A method of manufacturing a silicon carbide semiconductor device includes formation of an electrode and formation of a gate wiring. The electrode is formed to be electrically connected to a base layer and an impurity region included in a semiconductor substrate through a first contact hole. The gate wiring is formed to be electrically connected to a connection wiring through a second contact hole, and is made of material capable of deoxidizing an oxide film. The oxide film is removed by deoxidizing the oxide film formed on the connection wiring to remove the oxygen from the oxide film into the gate wiring through heating treatment for the gate wiring in the formation of the gate wiring or after the formation of the gate wiring.

A semiconductor device includes; a semiconductor substrate; an emitter electrode provided on the semiconductor substrate; a gate electrode provided on the semiconductor substrate; a drift layer of a first conduction type provided in the semiconductor substrate; a source layer of the first conduction type provided on an upper surface side of the semiconductor substrate; a base layer of a second conduction type provided on the upper surface side of the semiconductor substrate; a collector electrode provided below the semiconductor substrate; and a two-part dummy active trench including, at an upper part, an upper dummy part not connected with the gate electrode and including, at a lower part, a lower active part connected with the gate electrode and covered by an insulating film, in a trench of the semiconductor substrate, wherein a longitudinal length of the lower active part is larger than a width of the lower active part.