Provided is a novel power conversion device that enables estimation of a temperature of a power device without using a temperature sensing diode and can accurately estimate a temperature and a current of a current sensing element that observes a main current. A measurement voltage (Vref) is applied between source terminals (31s and 49s) of a main control element 31 and a current sensing element 49 in a state in which the main control element 31 and the current sensing element 49 are turned off, and a temperature of a power device 30 is estimated from a current (Ib) flowing between the source terminals (31s and 49s) of the main control element 31 and the current sensing element 49 at the time of the application by using the fact that a resistance value of a semiconductor substrate between the source terminals of the main control element 31 and the current sensing element 49 has temperature dependency.

A semiconductor device includes: a semiconductor body having a first surface, a second surface opposite to the first surface in a vertical direction, an active region, and a sensor region arranged adjacent to the active region in a horizontal direction; transistor cells at least partly integrated in the active region, each transistor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; at least one sensor cell at least partly integrated in the sensor region, each sensor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; and an intermediate region arranged between the active region and the sensor region, the intermediate region including a drift region and an undoped semiconductor region extending from the first surface into the drift region.

A main semiconductor device element is SiC-MOSFETs with a trench gate structure, the main semiconductor device element having main MOS regions responsible for driving the MOSFETs and main SBD regions that are regions responsible for SBD operation. The main MOS regions and the main SBD regions are adjacent to one another and each pair of a main MOS region and a main SBD region adjacent thereto share one trench. In the main SBD regions, first and second p-type regions, and Schottky electrodes at the front surface of the semiconductor substrate and forming Schottky junctions with an n.sup.−-type drift region are provided. The first p-type regions are provided along sidewalls of the trenches, in contact with the first p.sup.+-type regions at the bottoms of the trenches. The second p-type regions are provided between the first p-type regions and the Schottky electrodes, and are electrically connected to these regions.

A semiconductor device includes a semiconductor layer that has a main surface, a main surface electrode that is arranged at the main surface, an insulating film that partially covers the main surface electrode such as to expose a portion of the main surface electrode, a mold layer that covers the insulating film such as to expose the main surface electrode, and a pad electrode that is arranged on the main surface electrode such as to be electrically connected to the main surface electrode.

A semiconductor device according to the present disclosure includes a sense source electrode provided separately from a source electrode, and diodes. The diodes are provided between the sense source electrode and a drift layer. A turn-on voltage of each diode is lower than an operating voltage of a p-n diode formed of a sense well region and the drift layer or of a dummy sense well region and the drift layer. The diodes allow a current to flow from the sense source electrode toward a drain electrode. The diodes are provided in such a way that they are mixed with facing areas in a dummy sense region in which dummy sense well regions and the diodes are disposed. Each facing area is an area where one of the dummy sense well regions faces one of the gate electrodes via one of the gate insulating films.

In a semiconductor device, vertical semiconductor switching elements having a same structure are provided in a main cell region and a sense cell region. The sense cell region is defined as a quadrangular region surrounding an operating region of the semiconductor switching element formed as a sense cell, with (i) a lateral dimension of the sense cell region defined along one direction of the main cell region, and (ii) a longitudinal dimension of the sense cell region defined along a longitudinal direction that is orthogonal to the lateral direction. The longitudinal dimension of the sense cell region is equal to or greater than the lateral dimension of the sense cell region.

A semiconductor device has a cell portion and a peripheral portion. The cell portion includes a semiconductor substrate, a first impurity region, a second impurity region, and a contact region for the second impurity region. The semiconductor substrate has a drift layer. The first impurity region is on the drift layer. The second impurity region is on a surface layer portion of the first impurity region. A length of the cell portion is identical to a length of the second impurity region in one direction. The contact region extends from the cell portion to the peripheral portion. A length of a section of the contact region at the peripheral section in the one direction is defined as a protruding length, and a length of the second impurity region is defined as a second-impurity-region length. A ratio of the protruding length to the second-impurity-region length is 0.1 or smaller.

An electric assembly includes an insulated gate bipolar transistor device, a wide-bandgap transistor device electrically connected in parallel with the bipolar transistor device and a control circuit. The control circuit is electrically coupled to a gate terminal of the bipolar transistor device and to a control terminal of the wide-bandgap transistor device. The control circuit is configured to turn on the bipolar transistor device and to turn on the wide-bandgap transistor device at a predefined turn-on delay with respect to a turn-on of the bipolar transistor device.

What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

A semiconductor device includes a cell portion and a peripheral portion. The cell portion has a semiconductor element including a drift layer, a first impurity region, a second impurity region, trench-gate structures, a high-concentration layer, an interlayer insulating film, a first electrode and a second electrode. The interlayer insulating film is located on the trench-gate structures, the first impurity region and the second impurity region, and has a first contact hole communicating with the first impurity region and the second impurity region. The peripheral portion has a section facing the cell portion in one direction, and the interlayer insulating film further has a second contact hole at the section of the peripheral portion. The second contact hole exposes the first impurity region, and the first electrode is electrically connected to the first impurity region through the second contact hole in the peripheral portion.