A semiconductor device includes: a substrate; a source region and a drain region located in the substrate; a gate structure located in the substrate between the source region and the drain region; an insulating layer located between the gate structure and the drain region; a plurality of field plates located on the insulating layer, wherein the field plate closest to the gate structure is electrically connected to the source region; a first well region located in the substrate; a body contact region located in the first well region, wherein the body contact region is electrically connected to the source region and the field plate closest to the gate structure; and a first doped drift region located in the substrate, wherein the gate structure is located between the first well region and the first doped drift region, and the drain region is located in the first doped drift region.

A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

A laterally diffused metal oxide semiconductor device can include: a well region having a second doping type; a reduced surface field effect layer of a first doping type formed by an implantation process in a predetermined region of the well region, where a length of the reduced surface field effect layer is less than a length of the well region; a body region of the first doping type extending from a top surface of the well region into the well region; a drain portion of the second doping type extending from the top surface of the well region into the well region; and an insulating structure located between the body region and the drain portion, at least a portion of the insulating structure is located on the top surface of the well region.

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.

A power transistor having: a p-body region, coupled to a first voltage; a first p-type buried layer under the p-body region; a n-implant region surrounding the p-body region and the p-type buried layer; a p-implant region surrounding the n-implant region; and a p-implant guard ring region inserted into the n-implant region to split the n-implant region to a first part and a second part, wherein the first part of the n-implant region is between the p-body region and the p-implant guard ring region, and the second part of the n-implant region is between the p-implant guard ring region and the p-implant region; wherein the second part of the n-implant region has a Schottky contact region coupled to a second voltage via a metal contact.

The present disclosure provides a semiconductor device capable of reducing wiring resistance by using a stripe wire. The semiconductor device includes: a source pad electrode formed on a second interlayer insulating layer; a plurality of source extraction electrodes extracted in a first direction from the source pad electrode; a drain pad electrode formed on the second interlayer insulating layer; and a plurality of drain extraction electrodes extracted in the first direction from the drain pad electrode. The source pad electrode and the plurality of source extraction electrodes are electrically connected to a plurality of source wires of stripe wire covered by the second interlayer insulating layer. The drain pad electrode and the plurality of drain extraction electrodes are electrically connected to a plurality of drain wires of the stripe wire. The plurality of drain extraction electrodes are engaged with the plurality of source extraction electrodes.

An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.

A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.