Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a bulk substrate having an upper surface, a semiconductor layer above the bulk substrate, an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region on the bulk substrate, the source region and the drain region are raised above the upper surface of the bulk substrate, in which the source region and the drain region include an epitaxial semiconductor material, a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer, and a gate electrode above the gate dielectric.

A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

The method of manufacturing an integrated circuit includes obtaining a silicon carbide substrate of a first conductivity type having an epitaxial layer of a second conductivity type thereon. A dopant is implanted in the epitaxial layer to form a first region of the first conductivity type that extends the full depth of the epitaxial layer. A first transistor is formed in the first region and a second transistor is formed in the epitaxial layer.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.

The method of manufacturing an integrated circuit includes obtaining a silicon carbide substrate of a first conductivity type having an epitaxial layer of a second conductivity type thereon. A dopant is implanted in the epitaxial layer to form a first region of the first conductivity type that extends the full depth of the epitaxial layer. A first transistor is formed in the first region and a second transistor is formed in the epitaxial layer.

A semiconductor device includes a silicon-on-insulator (SOI) substrate and transistor cells electrically coupled in parallel to form a power transistor. Each transistor cell includes a source region in a silicon layer of the SOI substrate, a body region in the silicon layer and adjoining the source region, a gate structure configured to control a channel within the body region, a drain region in the silicon layer, and a drift region laterally separating the body region from the drain region. Each gate structure includes a gate electrode separated from the silicon layer by a gate dielectric having a thickness in a range of 20 nm to 60 nm. An effective length of the channel of each transistor cell is in a range of 50 nm to 500 nm. The power transistor has a maximum rated voltage in a range of 5V to 60V. Corresponding methods of producing the semiconductor device are also described.

A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure which has a first corner. The semiconductor device also includes a first well region with a first conductive type. The semiconductor device includes further includes a gate structure over the first well region and covers a portion of the first corner of the first isolation structure. In addition, the semiconductor device includes a first doped region and a second doped region disposed on two opposites of the gate structure. Each of the first doped region and the second doped region has the first conductive type. The semiconductor device also includes a first counter-doped region in the first well region with a second conductive type different from the first conductive type. The first counter-doped region covers the first corner of the first isolation structure.