A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

An electric circuit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor in a common semiconductor substrate. The first transistor is of the same conductivity type as the second transistor. A first source region of the first transistor is electrically connected to a first source terminal via a first main surface of the semiconductor substrate. A second drain region of the second transistor is electrically connected to a second drain terminal via a first main surface of the semiconductor substrate. A first drain region of the first transistor and a second source region of the second transistor are electrically connected to an output terminal via a second main surface of the semiconductor substrate. The electric circuit further includes a control circuit operable to control a first gate electrode of the first transistor and a second gate electrode of the second transistor.

A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first direction parallel to a first main surface of a semiconductor substrate. The semiconductor device further includes a layer stack having a drift layer of the first conductivity type and a compensation layer of a second conductivity type. The drain region is electrically connected with the drift layer. The semiconductor device also includes a connection region of the second conductivity type extending into the semiconductor substrate, the connection region being electrically connected with the compensation layer, wherein the buried semiconductor portion does not fully overlap with the drift layer.

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.

Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.

A MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the semiconductor substrate and the epitaxial layer. In a p-type body layer provided in a surface portion of the epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the epitaxial layer in spaced relation from the body layer. An n-type drain layer is provided in a surface portion of the epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the epitaxial layer between the drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer.

A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film.

A laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region is provided. A first semiconductor region is formed over a second semiconductor region and with a first doping type. The second semiconductor region has a second doping type different than the first doping type. A gate electrode is formed laterally adjacent to the first semiconductor region and extending along a side boundary of the first semiconductor region. A first source/drain contact region and a second source/drain contact region are respectively formed on opposite sides of the gate electrode and with the second doping type. The first source/drain contact region is further formed over the first semiconductor region. A method for manufacturing the LDMOS transistor is also provided.

One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.