A wide bandgap semiconductor device includes a chip that includes a wide bandgap semiconductor and that has a main surface, a main surface electrode arranged on the main surface, and a thermosetting resin that includes a matrix resin and a plurality of fillers and that covers the main surface such as to expose a part of the main surface electrode.

A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.

In a semiconductor device, a semiconductor substrate has an element region and a peripheral region, and trenches are defined on an upper surface of the semiconductor substrate. The trenches extend in a first direction, and are arranged at intervals in a second direction. The element region includes an n-type source region, a p-type contact region, a p-type body region, an n-type drift region, a p-type bottom region, and p-type connection regions. The bottom region is spaced from a bottom surface of the trenches. The connection regions connect the body region and the bottom region, extend in the first direction, and are arranged at intervals in the second direction. The element region has outer side portions and a central portion in the second direction. An interval between the connection regions in the second direction is greater in the outer side portion than in the central portion.

A transistor is disclosed. In an embodiment a transistor includes a first semiconductor region of a substrate, a first trench delimiting the first semiconductor region on a first side, a first electrically-conductive element located in the first trench, a channel area in contact with the first semiconductor region and a first area of contact with the first semiconductor region, wherein the channel area and the first area of contact are on the same surface side of the substrate.

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etched to form a plurality of gate extension trenches extending outward from the gate base recess; forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and forming a source region and a drain region on opposing sides of the gate electrode.