Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.

A processor-implemented method performed by an electronic apparatus includes determining a second voltage obtained by reducing a first voltage by a voltage having a preset magnitude, controlling a target semiconductor chip such that the target semiconductor chip performs a preset target task based on the second voltage, determining whether a result of the target task is the same as a reference result preset for the target task, and determining the first voltage as being a low supply voltage of the target semiconductor chip, in response to the result differing from the reference result.

A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.

An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.

It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.

A drive device includes: a first current path that has a high-side MOSFET; a second current path that has a low-side MOSFET; and a third current path connected to the other end portion of a coil and positioned between the first current path and the second current path. The drive device further includes: PWM drive circuits that generate a drive signal through PWM control; and an overcurrent detection circuit that detects that an overcurrent has flowed through the current paths. It is possible to precisely detect the occurrence of a battery short circuit and a ground short circuit by detecting which of the first current path and the second current path an overcurrent has flowed through.

An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

A level shifter circuit uses standard n-channel and p-channel transistors except for a pair of Lateral-Diffusion Metal-Oxide-Semiconductor (LDMOS) transistors that have an added lateral diffusion under the gate between the source and the conduction channel, increasing the breakdown voltage. The source of each LDMOS transistor connects to a drain of a transient differential transistor that has its gate driven by a oneshot that generates a pulse after an input transition. After the pulse ends a holding differential transistor draws a smaller bias current from the LDMOS transistors. The source of each LDMOS transistor connects to the drain and gate of a p-channel sensing transistor that drives gates of mirror transistors generating mirrored currents to cross-coupled n-channel mirror transistors that drive both terminals of a bistable latch that holds the output using a floating ground between driver transistors of a Buck converter switched by the bistable latch.

A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.