A power stage, comprising of multiple power MOSFETs and control and monitoring circuits, is an important part of voltage regulators. The voltage regulator controller typically monitors the power stage output current to implement control and protection functions. Traditional power stages mostly adapt monolithic solutions, suffering from performance inefficiencies due to the LDMOS process, while co-packaged solutions with combined VDMOS and LDMOS processes suffer from potential large current monitoring errors due to different operating temperatures. The current invention proposes a current monitoring circuit with temperature compensation to cancel the temperature coefficient mismatch between the external power MOSFET and the current monitoring circuit. Therefore, the gain of the current monitoring circuit doesn't change with the temperature, allowing for high current monitoring precision, and the temperature compensation circuit doesn't affect the bandwidth of the current monitoring circuit, allowing the use of the output current monitoring signal for close-loop control and over-current protection.

It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.

A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a source contact, the source contact including a first and second source contact portion, and a gate electrode in a gate trench in the first main surface adjacent to a body region. The body region and a drift zone are disposed along a first direction parallel to the first main surface between the source region and a drain region. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region, the first source contact portion further including a portion of the semiconductor substrate between the source conductive material and the second source contact portion. The semiconductor device further includes a temperature sensor in the semiconductor substrate.

A drive device includes: a first current path that has a high-side MOSFET; a second current path that has a low-side MOSFET; and a third current path connected to the other end portion of a coil and positioned between the first current path and the second current path. The drive device further includes: PWM drive circuits that generate a drive signal through PWM control; and an overcurrent detection circuit that detects that an overcurrent has flowed through the current paths. It is possible to precisely detect the occurrence of a battery short circuit and a ground short circuit by detecting which of the first current path and the second current path an overcurrent has flowed through.

A lateral semiconductor field-effect transistor (FET) device fabricated on a substrate includes a high-voltage main FET having interdigitated, elongated source and drain electrode fingers each of which is electrically connected to a respective interdigitated, elongated source and drain region disposed in the substrate. The FET device further includes first and second sense FETs each having a drain region in common with the high-voltage main FET. The sense FETS also include respective first and second elongated source electrode fingers each of which is electrically connected to respective first and second elongated source regions of the first and second sense FETs, respectively. The first and second elongated source electrode fingers are disposed length-wise adjacent to one of the elongated drain electrode fingers. The first elongated source finger has a first length, and the second elongated source finger has a second length, the second length being less than the first length.