A device includes a semiconductive fin, an isolation structure, a gate structure, dielectric spacers, and source/drain epitaxial structures. The isolation structure surrounds a bottom portion of the semiconductive fin. The gate structure is over the semiconductive fin. The dielectric spacers are on opposite sides of the semiconductive fin and over the isolation structure. The dielectric spacers include nitride. The source/drain epitaxial structures are on opposite sides of the gate structure and over the dielectric spacers. The source/drain epitaxial structures have hexagon shapes.

The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T.sub.1 of the cap portion is greater than a thickness T.sub.2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

Methods and semiconductor structures are provided. A method according to the present disclosure includes depositing a top epitaxial layer over a substrate, forming a fin structure from the top epitaxial layer and a portion of the substrate, recessing a source/drain region of the fin structure to form a source/drain recess, conformally depositing a semiconductor layer over surfaces of the source/drain recess, etching back the semiconductor layer to form a diffusion stop layer over a bottom surface of the source/drain recess, depositing a first epitaxial layer over the diffusion stop layer and sidewalls source/drain recess, depositing a second epitaxial layer over the first epitaxial layer, and depositing a third epitaxial layer over the second epitaxial layer. A germanium concentration of the diffusion stop layer is greater than a germanium concentration of the top epitaxial layer or a germanium concentration of the first epitaxial layer.

Provided are metal oxide field-effect transistor (MOSFET) devices having a metal gate structure, in which a work function of the metal gate structure is uniform along a length direction of a channel, and manufacturing methods thereof. The MOSFET devices include a semiconductor substrate, an active area on the semiconductor substrate and extending in a first direction, and a gate structure on the semiconductor substrate. The gate structure extends across the active area in a second direction that traverses the first direction and comprises a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area. A lower surface of the WFC layer may be longer than a first interface between a lower surface of the first metal layer and an upper surface of the high-k layer in the first direction.

Disclosed are a semiconductor structure and a forming method thereof. In one form, a forming method includes: providing a base, including a substrate and a plurality of fins protruding from the substrate, an interlayer dielectric layer formed on the substrate, a gate opening formed in the interlayer dielectric layer, the gate opening spanning the fin and exposing a part of a top and a part of a sidewall of the fin, and a source/drain doped region formed in the fins on two sides of the gate opening, where the substrate includes a first region and a second region adjacent to each other, to respectively form transistors, the gate opening located in either of the first region and the second region extends to the other region and exposes the fin of the other region, and a position of the exposed fin of the other region is used as an interconnect position; forming a gate dielectric layer covering a bottom and a sidewall of the gate opening and the fin in the gate opening conformally; removing the gate dielectric layer on a surface of the fin at the interconnect position, to expose the surface of the fin at the interconnect position; and forming a gate structure in the gate opening after the surface of the fin at the interconnect position is exposed. The present disclosure enlarges a process window for electrical connection.

There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a first gate dielectric on a first channel region of the first semiconductor fin, the first gate dielectric including a first interfacial layer and a first high-k dielectric layer; a second semiconductor fin protruding above the isolation region; and a second gate dielectric on a second channel region of the second semiconductor fin, the second gate dielectric including a second interfacial layer and a second high-k dielectric layer, a first portion of the first interfacial layer on the first channel region having a greater thickness than a second portion of the second interfacial layer on the second channel region, the second channel region having a greater height than the first channel region.

The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.

A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.