A memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer; a first conductive layer, a second insulating layer; a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate; wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; using a photomask to apply a photoresist to cover a first part of the second dielectric layer; removing a second part of the second dielectric layer while retaining the first part of the second dielectric layer; and removing the photoresist. The first part of the second dielectric layer covers a first part of the first dielectric layer in a first area. The second part of the second dielectric layer covers a second part of the first dielectric layer in a second area. The first area is corresponding to a memory device. The second area is corresponding to a logic device.

A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

A memory device is provided. The device comprises a semiconductor fin with a first gate and a second gate disposed over the semiconductor fin. A third gate is positioned over the semiconductor fin and a lower portion of the third gate is disposed between the first and second gates.

A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.

Certain aspects of the present disclosure are generally directed to non-volatile memory (NVM) and techniques for operating and fabricating NVM. Certain aspects provide a memory cell for implementing NVM. The memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions. The memory cell also includes a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region, a first front gate region disposed adjacent to the second semiconductor region, and a first floating front gate region disposed adjacent to the third semiconductor region. In certain aspects, the memory cell includes a back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region.

A flash memory device includes a first memory cell, a second memory cell, a row decoder, and a bias generator. The first memory cell is a selected memory cell, and the second memory cell is an unselected memory cell connected with a bit line that is connected to the first memory cell. The row decoder controls a word line voltage to be applied to the first memory cell and controls an unselected source line voltage to be applied to the second memory cell. The bias generator generates the word line voltage based on a threshold voltage of a word line transistor changing with an ambient temperature and generates the unselected source line voltage based on a voltage level of the selected bit line.