A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.

A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

A method is provided for forming a split-gate memory cell having field enhancement regions in the substrate for improved cell performance. The method may include forming a pair of gate structures over a substrate, performing a source implant between the pair of gate structures to form a self-aligned source implant region in the substrate, performing a field enhancement implant process to form field enhancement implant regions, e.g., having an opposite dopant polarity as the source implant, at or adjacent lateral sides of the source implant region, and diffusing the source implant region and field enhancement implant regions to thereby define a source region with field enhanced regions at lateral edges of the source region. The field enhanced implant process may include at least one non-vertical angled implant.

A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

A memory device includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, a first floating gate structure, a second floating gate structure, a first word line, a common source, a second word line, a first spacer and a second spacer. The first floating gate structure and the second floating gate structure are recessed in the substrate at two opposite sides of the erase gate structure. The first word line and the second word line are respectively adjacent to the first floating gate structure and the second floating gate structure. The common source is disposed in the substrate under the erase gate structure. The first word line and the second word line may be metal gates of high-k metal gate structures.

A flash memory device includes a first memory cell, a second memory cell, a row decoder, and a bias generator. The first memory cell is a selected memory cell, and the second memory cell is an unselected memory cell connected with a bit line that is connected to the first memory cell. The row decoder controls a word line voltage to be applied to the first memory cell and controls an unselected source line voltage to be applied to the second memory cell. The bias generator generates the word line voltage based on a threshold voltage of a word line transistor changing with an ambient temperature and generates the unselected source line voltage based on a voltage level of the selected bit line.

In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.